View ISL8272MBIRZ_9004536.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fn8670 rev.5.00 nov 8, 2017 isl8272m 50a digital dc/dc pmbus power module datasheet fn8670 rev.5.00 page 1 of 59 nov 8, 2017 the isl8272m is a 50a step-down pmbus compliant digital power module. integrated in the module is a high performance digital pwm controller, dual-phase power mosfets, inductors, and the passives. this high efficiency power module is capable of delivering 50a without the ne ed for airflow and heatsinks. the isl8272m can be placed in a current sharing configuration with up to four modules in parallel to deliver 200a continuous current. the isl8272m operates with the chargemode? control architecture, which responds to a transient load within a single switching cycle. the isl8272m comes with operating in a pin strap mode; output voltage, switching frequency device, smbus address, input uvlo, soft-start/stop, and current sharing can be programmed through external resi stors. more configuration such as fault limits, fault response, margining, and sequencing can be easily programmed using the pmbus interface. pmbus can be used to monitor voltages, currents, temperatures, and fault status. the isl8272m is supported by the powernavigator? software, a graphical user interface (gui) that can be used to configure modules to a desired solution. the isl8272m is built in a compact (18mmx23mmx7.5mm) and low profile overmolded hda package, suitable for automated assembly by standard surface mount equipment. features ? complete digital switch mode power supply ? wide input voltage range: 4.5v to 14v ? programmable output voltage range: 0.6v to 5v ? pmbus compliant communication interface ?programmable v out , margining, uv/ov, uc/oc, ut/ot, soft-start/stop, sequencing and external synchronization ? monitor of v in , v out , i out , temperature, duty cycle, switching frequency, power-good, and faults ? fast response chargemode control architecture ? multiphase current sharing with up to four modules ?1.0% v out accuracy over line, load, and temperature ? internal nonvolatile memory and fault logging ? thermally enhanced hda package applications ? server, telecom, storage, and datacom ? industrial/ate and networking equipment ? general purpose power for asic, fpga, dsp, and memory related literature ? for a full list of related documents, visit our website - isl8272m product page figure 1. 50a application circuit figure 2. a small package for high power density vin vdd vr55 vr5 vr vout sgnd pgnd vr6 vdrv scl sda salrt vmon vcc vdrv1 vsenp vsenn vin cin isl8272m vout pmbus interface cout 100k 2x10f 10f 10f ?? en enable 6.65k ?? note: 1. figure 1 represents a typical implementation of the isl8272m. for pmbus operation, it is recommended to tie the enable pin (en) to sgnd. 2 3 m m 1 8 m m 7.5mm
isl8272m fn8670 rev.5.00 page 2 of 59 nov 8, 2017 table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 isl8272m internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical application circuit - single module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical application circuit - three module current sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 efficiency performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 transient response performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 derating curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 smbus communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 soft-start/stop delay and ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 switching frequency and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 input undervoltage lockout (uvlo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 smbus module address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output overvoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output prebias protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 thermal overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 digital-dc bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 active current sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 phase spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 fault spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 output sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 monitoring with smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 snapshot parameter capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 nonvolatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 layout guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 pcb layout pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 thermal vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 stencil pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 reflow parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 pmbus command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 pmbus data formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 pmbus use guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 pmbus commands description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 firmware revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
isl8272m fn8670 rev.5.00 page 3 of 59 nov 8, 2017 ordering information part number ( notes 2 , 3 , 4 ) part marking temp range (c) package (rohs compliant) pkg. dwg. # isl8272mairz isl8272m -40 to +85 58 ld 18x23 hda y58.18x23 ISL8272MBIRZ isl8272mb -40 to +85 58 ld 18x23 hda y58.18x23 isl8272meval1z single-module evaluation board (see ug003 , ?isl8272meval1z evaluation board user guide?) isl8272meval2z three-module current sharing evaluation board (see ug004 , ?isl8272meval2z evaluation board user guide?) notes: 2. add ?-t? suffix for 100 unit tape and reel option. refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged prod ucts are rohs compliant by eu exemption 7c-i and 7a. they employ special pb-free material sets; molding compounds/die attach materials and nipdau pl ate-e4 termination finish, which is compat ible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak refl ow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std- 020. 4. for moisture sensitivity level (msl), refer to the isl8272m product information page. for more information about msl, refer to tb363 . isl xxxxm f t r z s intersil ? device ? designator base ? part ? number firmware ? revision a: ? fc01 b: ? fc02 operating ? temperature i: ? industrial ? ( \? 40c ? to ? +85c) shipping ? option blank: ? bulk t: ? tape ? and ? reel rohs z: ? rohs ? compliant package ? designator r: ? high ? density ? array ? (hda)
isl8272m fn8670 rev.5.00 page 4 of 59 nov 8, 2017 pin configuration isl8272m (58 ld hda) top view a b c d e f g h j k l m n p r t u v w y aa ab ac 1 2 3 4 5 6 7 8 9 101112131415161718 pad1 pad2 pad8 pad9 pad10 pad11 pad12 pad6 pad13 pad14 pad15 pad16 pad3 pad4 pad5 pad7 vout vout pgnd pgnd pgnd pgnd pgnd pgnd sgnd sgnd sgnd sw1 sw2 vin vin vin dcm dcm swd2 vdrv pgnd pgnd swd1 vr vcc vsenp vsenn test test ddc ss/uvlo pg vset test cs mgn sa salrt sda scl vmon sync test en test test v25 ascr sgnd vdd vr5 sgnd vr6 vdrv pgnd vr55 pgnd pgnd vdrv1 vdrv1 pin descriptions pin label type description pad1, 2 vout pwr power supply output voltage. output voltage from 0.6v to 5v. tie these two pins together to achieve a single outp ut. for higher output voltage, refer to the derating curves starting on page 15 to set the maximum output current from these pads. pad3, 4, 5, 7, 10, 12, 13, 15 pgnd pwr power ground. refer to ? layout guide ? on page 23 for the pgnd pad connections and i/o capacitor placement. pad6 sgnd pwr signal ground. refer to ? layout guide ? on page 23 for the sgnd pad connections. pad8, 9, 11 vin pwr input power supply voltage to power the module. input voltage range from 4.5v to 14v. pad14, 16 sw1, sw2 pwr switching node pads. the sw pads dissipate the he at and provide good thermal performance. refer to ? layout guide ? on page 23 for the sw pad connections. c6 vset i output voltage selection pin. used to set v out set point and v out max. c7 cs i current sharing configuration pin. used to program curre nt sharing configurations such as sync selection, phase spreading, and v out droop. c8 mgn i external v out margin control pin. active high (>2v) sets v out margin high; active low (<0.8v) sets v out margin low; high impedance (floating) sets v out to normal voltage. factory defaul t range for margining is nominal v out 5%. when using pmbus to control margin comm and, leave this pin as no connection. c9 vmon i driver voltage monitoring. use this pin to monitor vdrv through an external 16:1 resistor divider. c10 sa i serial address selection pin. used to assign unique address for each in dividual device or to enable certain management features. c11 salrt o serial alert. connect to external host if desired. salr t is asserted low upon a warning or a fault event and deasserte d when warning or fault is cleared. a pull-up resistor is required.
isl8272m fn8670 rev.5.00 page 5 of 59 nov 8, 2017 c12 sda i/o serial data. connect to external host and/or to other digital-dc? devices. a pull-up resistor is required. c13 scl i/o serial clock. connect to external host and/or to other digital-dc devices. a pull-up resistor is required. d4 ss/ uvlo i soft-start/stop and undervoltage lockout selection pin. used to set turn on/off delay and ramp time as well as input uvlo threshold levels. d5 pg o power-good output. power-good output can be an open drai n that requires a pull-up resistor or push-pull output that can drive a logic input. d13 sync i/o clock synchronization input. used to set the frequency of the internal switch clock, to sync to an external clock or to output internal clock. e14 en i enable pin. logic high to enable the module output. e4 ddc i/o a digital-dc bus. this dedicated bus provides the co mmunication between devices for features such as sequencing, fault spreading and current sharing. the ddc pin on all di gital-dc devices should be connected together. a pull-up resistor is required. c5, d14, e15, f4, f15, g4 test - test pins. do not connect these pins. g14 ascr i chargemode? control ascr parameters selection pin. used to set ascr gain and residual values. g15 v25 pwr internal 2.5v reference used to power internal circuitry. no external capacitor required for this pin. h3 vsenn i differential output voltage sense feedback . connect to negative output regulation point. h4 vsenp i differential output voltage sense feedback . connect to positive output regulation point. h16, j16, k16, m14 sgnd pwr signal grounds. using multiple vias to co nnect the sgnd pins to the internal sgnd layer. k14 vdd pwr input supply voltage for controller. connect vdd pad to v in supply. l2 vr pwr internal ldo bias pin. tie vr to vr55 directly with a short loop trace. l3, p11 swd1, swd2 pwr switching node driving pins. directly connect to the sw1 and sw2 pads with short loop wires. l14 vr5 pwr internal 5v reference used to power internal ci rcuitry. place a 10f decoup ling capacitor for this pin. m1 vcc pwr internal ldo output. connect vcc to vdrv for internal ldo driving. m5, m17, n5 pgnd pwr power grounds. using multiple vias to connect the pgnd pins to the internal pgnd layer. m10 vr55 pwr internal 5.5v bias voltage for internal ldo use only. tie vr55 pin directly to vr pin. m13 vr6 pwr internal 6v reference used to power internal ci rcuitry. place a 10f decoup ling capacitor for this pin. n6, n16 vdrv pwr power supply for internal fet drivers. connect 10 f bypass capacitor to each of these pins. these pins can be driven by the internal ldo through vcc pin or by the external po wer supply directly. keep the driving voltage between 4.5v and 5.5v. for 5v input application, use ex ternal supply or connect this pin to vin. r8, r17 vdrv1 i bias pin of the internal fet drivers. always tie to vdrv. pin descriptions (continued) pin label type description
isl8272m fn8670 rev.5.00 page 6 of 59 nov 8, 2017 isl8272m internal block diagram digital controller pgnd sgnd vset scl salrt sa en pg sync sgnd pwm2 pmbus/i 2 c interface sda adc csa vsa supervisor internal temp sensor protection oc/uc d-pwm pll sync out power management ss margining ov/uv current share interleave sequence nvm vdd ddc snapshot fault spreading ot/ut vout 0.27h logic vin pgnd vin vdrv vr6 vsenp mgn vmon adc vr5 v25 ldos vr55 vdd filter vout 0.27h logic vin pgnd csa chargemode tm control adc pwm1 vr vdrv1 vdrv1 vdrv vdrv vcc ss/uvlo ascr cs vdrv1 swd2 sw2 swd1 sw1 vsenn ldo adc 22 ?? 22 ?? figure 3. internal block diagram
fn8670 rev.5.00 page 7 of 59 nov 8, 2017 isl8272m typical application circuit - single module figure 4. typical applicatio n circuit - single module vin vdd vr55 vr5 vr vout sgnd pgnd vr6 vdrv scl sda salrt vmon vcc vdrv1 vsenp vsenn vin vcc isl8272m vout 1.2v 50a 10f 10f 10f sa vset en cs ss/uvlo ascr vaux or vcc 3.3v to 5v ddc sync mgn swd1 sw1 swd2 sw2 12v 10f 470f bulk 4x22f ceramic 8x100f ceramic 4x470f poscap scl pin strap resistors (optional) en mgn sda salrt ddc c 1 c 2 c 3 c 4 c 5 c 6 c 7 10f c 8 c 9 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 pg pg 10k ?? 10k ?? 10k ?? 10k ?? 100k ?? 6.65k ?? notes: 5. r 2 and r 3 are not required if the pmbus host already has i 2 c pull-up resistors. 6. only one r 4 per ddc bus is required when multiple modules share the same ddc bus. 7. r 7 through r 12 can be selected according to the tables for the pin-strap resistor setting in this document. if the pmbus configuration is chosen to overwrite the pin-strap configuration, r 8 through r 12 can be non-populated. 8. v25, vr and vr55 do not need external capacitors. v25 can be no connection. note 5 note 5 note 6 note 7
isl8272m fn8670 rev.5.00 page 8 of 59 nov 8, 2017 typical application circuit - three module current sharing figure 5. typical application circuit - three module current sharing vin vdd vr55 vr5 vr vout sgnd pgnd vr6 vdrv scl sda salrt vmon vcc vdrv1 vsenp vsenn vcc3 isl8272m 10f 10f 10f sa vset en cs ss/uvlo ascr ddc mgn swd1 sw1 swd2 sw2 10f 4x22f ceramic 4x100f ceramic pin strap resistors (optional) en mgn c 16 c 17 c 18 c 19 c 20 c 21 10f c 22 r 19 r 20 r 21 r 22 r 23 r 24 r 25 pg pg3 vin vdd vr55 vr5 vr vout sgnd pgnd vr6 vdrv scl sda salrt vmon vcc vdrv1 vsenp vsenn vcc2 isl8272m 10f 10f 10f sa vset en cs ss/uvlo ascr ddc sync mgn swd1 sw1 swd2 sw2 10f 4x22f ceramic 4x100f ceramic pin strap resistors (optional) en mgn c 9 c 10 c 11 c 12 c 13 c 14 10f c 15 r 12 r 13 r 14 r 16 r 17 r 18 pg pg2 vin vdd vr55 vr5 vr vout sgnd pgnd vr6 vdrv scl sda salrt vmon vcc vdrv1 vsenp vsenn vin vcc1 isl8272m vout 1.2v 150a 10f 10f 10f sa vset en cs ss/uvlo ascr vaux or vcc 3.3v to 5v ddc sync mgn swd1 sw1 swd2 sw2 12v 10f 2x470f bulk 4x22 f ceramic 4x100f ceramic 12x470 f poscap scl pin strap resistors (optional) en mgn sda salrt ddc c 1 c 2 c 3 c 4 c 5 c 6 c 7 10f c 8 c 23 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 pg pg1 sync sync 12x100 f ceramic c 24 r 15 56.2k smbus address = 0x2c smbus address = 0x2b smbus address= 0x2a 4.7k ?? 4.7k ?? 4.7k ?? 4.7k ?? ?? 100k ?? 6.65k ?? 100k ?? 6.65k ?? 61.9k ?? 100k ?? 6.65k ?? 51.1k ??
isl8272m fn8670 rev.5.00 page 9 of 59 nov 8, 2017 table 1. isl8272m design guide matrix and output voltage response v in (v) v out (v) c in (bulk) ( note 9 ) (f) c in (ceramic) (f) c out (bulk) (f) c out (ceramic) (f) ascr gain ( note 10 ) ascr residual ( note 10 ) p-p deviation (mv) recovery time ( s ) load step (a) ( note 11 ) freq. ( khz ) 5 1 1x470 6x47 4x470 12x100 220 90 50 20 0/25 300 5 1 1x470 4x47 4x470 8x100 550 100 45 15 0/25 533 12 1 1x470 6x22 4x470 12x100 220 90 55 22 0/25 300 12 1 1x470 4x22 4x470 8x100 550 100 50 15 0/25 533 5 1.8 1x470 6x47 4x470 8x100 200 90 60 25 0/25 300 5 1.8 1x470 4x47 2x470 6x100 250 90 70 20 0/25 533 12 1.8 1x470 6x22 4x470 8x100 220 90 70 20 0/25 300 12 1.8 1x470 4x22 2x470 6x100 280 100 70 20 0/25 533 5 2.5 1x470 6x47 2x470 6x100 120 90 100 30 0/25 300 5 2.5 1x470 4x47 2x470 4x100 250 90 80 20 0/25 533 12 2.5 1x470 6x22 2x470 6x100 110 90 100 20 0/25 300 12 2.5 1x470 4x22 2x470 4x100 220 90 100 15 0/25 533 5 3.3 1x470 6x47 2x470 4x100 100 90 120 50 0/25 300 5 3.3 1x470 4x47 2x470 4x100 220 90 100 30 0/25 533 12 3.3 1x470 4x22 2x470 4x100 220 90 100 10 0/25 533 12 5 1x470 6x22 2x470 4x100 230 90 120 10 0/25 533 notes: 9. c in bulk capacitor is optional only for energy buffer from the long input power supply cable. 10. ascr gain and residual are selected to ensure phase margin hi gher than 60 and gain margin higher than 6db at room temperatu re and full load (50a). 11. output voltage response is tested with load step slew rate higher than 100a/s. table 2. recommended input/output capacitor vendors value part number murata, input ceramic 47f, 16v, 1210 grm32er61c476me15l murata, input ceramic 22f, 16v, 1210 grm32er61e226ke15l taiyo yuden, input ceramic 47f, 16v, 1210 emk325bj476mm-t taiyo yuden, input ceramic 22f, 25v, 1210 tmk325bj226mm-t murata, output ceramic 100f, 6.3v, 1210 grm32er60j107m tdk, output ceramic 100f, 6.3v, 1210 c3225x5r0j107m avx, output ceramic 100f, 6.3v, 1210 12106d107mat2a sanyo poscap, output bulk 470f, 4v 4tpe470mcl sanyo poscap, output bulk 470f, 6.3v 6tpf470mah
isl8272m fn8670 rev.5.00 page 10 of 59 nov 8, 2017 absolute maximum rating s thermal information input supply voltage, vin pin . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 17v input supply voltage for controller, vdd pin . . . . . . . . . . . . . . -0.3v to 17v mosfet switch node voltage, sw1/2, swd1/2 . . . . . . . . . . . -0.3v to 17v mosfet driver supply voltage, vdrv, vdrv1 pin . . . . . . . . . -0.3v to 6.0v output voltage, vout pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to 6.0v internal reference supply voltage, vr6 pin . . . . . . . . . . . . . . -0.3v to 6.6v internal reference supply voltage, vr, vr5, vr55 pin. . . . . -0.3v to 6.5v internal reference supply voltage, v25 pin . . . . . . . . . . . . . . . . -0.3v to 3v logic i/o voltage for ddc, en, mgn, pg, ascr, cs sa, scl, sda, salrt, sync, ss/uvlo, vmon, vset . . . . . -0.3v to 6.0v analog input voltages for vsenp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v vsenn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . 2000v machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c110d) . . . . . . . . . . . . 750v latch-up (tested per jesd78c; class 2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 58 ld hda package ( notes 12 , 13 ). . . . . . 6.55 1.6 maximum junction temperature (plastic package) . . . . . . . . . . . .+125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to figure 30 recommended operating conditions input supply voltage range, v in . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 14v input supply voltage range for controller, v dd . . . . . . . . . . . 4.5v to 14v output voltage range, v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.6v to 5v output current range, i out(dc) ( note 16 ). . . . . . . . . . . . . . . . . . . 0a to 50a operating junction temperature range, t j . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 12. ? ja is measured in free air with the module mounted on an 6-laye r evaluation board 4.7x4.8inch in size with 2oz surface and 2oz bu ried planes and multiple via interconnects as specified in the isl8272meval1z evaluation board user guide. 13. for ? jc , the ?case temp? location is the center of the package underside. electrical specifications v in = v dd = 12v, f sw = 533khz, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. symbol parameter test conditions min ( note 14 ) typ max ( note 14 ) units input and supply characteristics i dd input supply current for controller v in = v dd = 12v, v out = 0v, module not enabled 40 50 ma v r6 6v internal reference supply voltage 5.5 6.1 6.6 v v r5 5v internal reference supply i vr5 <5ma 4.5 5.2 5.5 v v 25 2.5v internal reference supply 2.25 2.5 2.75 v vcc internal ldo output voltage 5.3 v i vcc internal ldo output current v in = v dd = 12v, v cc connected to vdrv, module enabled 50 ma v dd_read_res input supply voltage for controller read back resolution 10 bits v dd_read_err input supply voltage for controller read back total error ( note 17 ) pmbus read 2 %fs output characteristics v out_range output voltage adjustment range v in > v out + 1.8v 0.54 5.5 v v out_res output voltage set-point range configured using pmbus 0.025 % v out_accy output voltage set-point accuracy ( notes 15 , 17 ) includes line, load and temperature (-20c t a +85c) -1 +1 %v out v out_read_res output voltage read back resolution 10 bits v out_read_err output voltage read back total error ( note 17 ) pmbus read -2 +2 %v out i out_read_res output current read back resolution 10 bits
isl8272m fn8670 rev.5.00 page 11 of 59 nov 8, 2017 i out_range output current range ( note 16 ) 50 a i out_read_err output current read back total error pmbus read at max load. v out = 1v 3 a soft-start and sequencing t on_delay delay time from enable to v out rise configured using pmbus 2 5000 ms t on_delay_accy t on_delay accuracy 2 ms t on_rise output voltage ramp-up time configured using pmbus. single module standalone 0.5 100 ms t on_rise_accy output voltage ramp-up time accuracy single module standalone 250 s t off_delay delay time from disable to v out fall configured using pmbus 2 5000 ms t off_delay_accy t off_delay accuracy 2 ms t off_fall output voltage fall time configured using pmbus. single module standalone 0.5 100 ms t on_fall_accy output voltage fall time accuracy single module standalone 250 s power-good v pg_delay power-good delay configured using pmbus 0 5000 ms temperature sense t sense_range temperature sense range configurable using pmbus -50 150 ? c int_temp accy internal temperature sensor accuracy tested at +100c -5 +5 ? c fault protection v dd_uvlo_range v dd undervoltage threshold range measured internally 4.18 16 v v dd_uvlo_accy v dd undervoltage threshold accuracy ( note 17 ) 2 %fs v dd_uvlo_delay v dd undervoltage response time 10 s v out_ov_range v out overvoltage threshold range factory default 1.15v out v configured using pmbus 1.05v out v out_max v v out_uv_range v out undervoltage threshold range factory default 0.85v out v configured using pmbus 00.95v out v v out_ov/uv_accy v out ov/uv threshold accuracy ( note 15 ) -2 +2 % v out_ov/uv_delay v out ov/uv response time 10 s i limit_accy output current limit set-point accuracy ( note 17 ) tested at i out _oc_fault_limit = 50a 10 % fs i limit_delay output current fault response time ( note 18 ) factory default 3 t sw t junction over-temperature protection threshold (controller junction temperature) factory default 125 ? c configured using pmbus -40 125 ? c t junction_hys thermal protection hysteresis 15 ? c electrical specifications v in = v dd = 12v, f sw = 533khz, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating te mperature range, -40c to +85c. (continued) symbol parameter test conditions min ( note 14 ) typ max ( note 14 ) units
isl8272m fn8670 rev.5.00 page 12 of 59 nov 8, 2017 oscillator and switching characteristics f sw_range switching frequency range 296 1067 khz f sw_accy switching frequency set-point accuracy -5 +5 % ext_sync pw minimum pulse width required from external sync clock measured at 50% amplitude 150 ns ext_sync drift drift tolerance for external sync clock external sync clock equal to 500khz is not supported -10 +10 % logic input/output characteristics i logic_bias bias current at the logic input pins ddc, en, mgn, pg, sa, scl, sda, salrt, sync, uvlo, v mon , v set -100 +100 na v logic_in_low logic input low threshold voltage 0.8 v v logic_in_high logic input high threshold voltage 2.0 v v logic_out_low logic output low threshold voltage 2ma sinking 0.5 v v logic_out_high logic output high thresh old voltage 2ma sourcing 2.25 v pmbus interface timing characteristic f smb pmbus operating frequency 100 400 khz notes: 14. compliance to datasheet limits is assured by one or more me thods: production test, characte rization and/or design. controlle r is independently tested before module assembly. 15. v out measured at the termination of the vsenp and vsenn sense points. 16. the max load current is determined by the thermal ? derating curves ? on page 15 provided with this document. 17. ?fs? stands for full scale of recommended maximum operation range. 18. ?t sw ? stands for time period of operation switching frequency. electrical specifications v in = v dd = 12v, f sw = 533khz, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating te mperature range, -40c to +85c. (continued) symbol parameter test conditions min ( note 14 ) typ max ( note 14 ) units
isl8272m fn8670 rev.5.00 page 13 of 59 nov 8, 2017 typical performance curves efficiency performance operating condition: t a = +25c, no air flow. c out = 1340f. typical values are used unless otherwise noted. figure 6. efficiency vs output current at v in = 5v, f sw = 300khz for various output voltages figure 7. efficiency vs switching frequency at v in = 5v, i out = 50a for various output voltages figure 8. efficiency vs output current at v in = 9v, f sw = 300khz for various output voltages figure 9. efficiency vs switching frequency at v in = 9v, i out = 50a for various output voltages figure 10. efficiency vs output current at v in = 12v, f sw = 300khz for various output voltages figure 11. efficiency vs switching frequency at v in = 12v, i out = 50a for various output voltages 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 0 5 10 15 20 25 30 35 40 45 50 0.8v 1v 1.2v 1.8v 2.5v 3.3v i out (a) efficiency (%) 0.85 0.87 0.89 0.91 0.93 0.95 0.97 300 350 400 450 500 550 600 650 700 750 800 850 900 switching frequency (khz) efficiency (%) 1v 1.2v 1.8v 2.5v 3.3v 0.8v 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 0 5 10 15 20 25 30 35 40 45 50 0.8v 1v 1.2v 1.8v 2.5v 3.3v i out (a) efficiency (%) 5v 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0.98 300 350 400 450 500 550 600 650 700 750 800 850 900 switching frequency (khz) efficiency (%) 1v 1.2v 1.8v 2.5v 3.3v 0.8v 5v 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 0 5 10 15 20 25 30 35 40 45 50 0.8v 1v 1.2v 1.8v 2.5v 3.3v i out (a) efficiency (%) 5v 0.82 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0.98 300 350 400 450 500 550 600 650 700 750 800 850 900 switching frequency (khz) efficiency (%) 1v 1.2v 1.8v 2.5v 3.3v 0.8v 5v
isl8272m fn8670 rev.5.00 page 14 of 59 nov 8, 2017 transient response performance operating condition: v in = 12v, f sw = 533khz, i out = 0a/25a, i out slew rate > 100a/s, t a = +25c, no air flow. typical values are used unless otherwise noted. figure 12. 1v transient response. c out = 8x100f ceramic + 4x470f poscap figure 13. 1.8v transient response. c out = 6x100f ceramic + 2x470f poscap figure 14. 2.5v transient response. c out = 4x100f ceramic + 2x470f poscap figure 15. 3.3v transient response. c out = 4x100f ceramic + 2x470f poscap figure 16. 5v transient response. c out = 4x100f ceramic + 2x470f poscap typical performance curves (continued)
isl8272m fn8670 rev.5.00 page 15 of 59 nov 8, 2017 derating curves all of the following curves were plotted at t j = +115c. figure 17. 5v in to 1v out , f sw = 300khz figure 18. 12v in to 1v out , f sw = 300khz figure 19. 5v in to 1.8v out , f sw = 300khz figure 20. 12v in to 1.8v out , f sw = 300khz figure 21. 5v in to 2.5v out , f sw = 300khz figure 22. 12v in to 2.5v out , f sw = 300khz typical performance curves (continued) 0 10 20 30 40 50 60 40 50 60 70 80 90 100 110 120 temperature (c) 0lfm 200lfm 400lfm load current (a) 0 10 20 30 40 50 60 40 50 60 70 80 90 100 110 120 temperature (c) 200lfm 400lfm load current (a) 0lfm 40 50 60 70 80 90 100 110 120 temperature (c) 0lfm 200lfm 400lfm load current (a) 0 10 20 30 40 50 60 0 10 20 30 40 50 60 40 50 60 70 80 90 100 110 120 temperature (c) 0lfm 200lfm 400lfm load current (a) 0 10 20 30 40 50 60 40 50 60 70 80 90 100 110 120 temperature (c) 0lfm 200lfm 400lfm load current (a) 0 10 20 30 40 50 60 40 50 60 70 80 90 100 110 120 temperature (c) 0lfm 200lfm 400lfm load current (a)
isl8272m fn8670 rev.5.00 page 16 of 59 nov 8, 2017 derating curves all of the following curves were plotted at t j = +115c. the read_internal_temp command value in the powernavigator tm software is the temperature reading value of the internal controller. the junction temperature of the power stage in the module may be higher than the read_internal_temp command value. the temperat ure difference depends on the operating conditions; in some extreme cases, the junction temperature of the power stage can be 30c higher than the read_internal_temp command value. figure 23. 5v in to 3.3v out , f sw = 300khz figure 24. 12v in to 3.3v out , f sw = 533khz figure 25. 12v in to 5v out , f sw = 533khz typical performance curves (continued) 0 10 20 30 40 50 60 40 50 60 70 80 90 100 110 120 temperature (c) 0lfm 200lfm 400lfm load current (a) 0 10 20 30 40 50 60 40 50 60 70 80 90 100 110 120 temperature (c) 0lfm 200lfm 400lfm load current (a) 0 10 20 30 40 50 60 40 50 60 70 80 90 100 110 120 temperature (c) 0lfm 200lfm 400lfm load current (a)
isl8272m fn8670 rev.5.00 page 17 of 59 nov 8, 2017 functional description smbus communications the isl8272m provides a pmbus digital interface that enables the user to configure all aspects of the module operation as well as monitor the input and output parameters. the isl8272m can be used with any smbus host device. in addition, the module is compatible with pmbus power system management protocol specification parts i and ii version 1.2. the isl8272m accepts most standard pmbus commands. when configuring the device with pmbus commands, it is recommended that the enable pin is tied to sgnd. the smbus device address is the only parameter that must be set by external pins. all other device parameters can be set with pmbus commands. the isl8272m can operate withou t the pmbus in pin-strap mode with configurations programmed by pin-strap resistors, such as output voltage, switching frequenc y, device smbus address, input uvlo, soft-start/stop, and current sharing. note: pin-strap resistors with 1% tolerance or be tter should be used for all the pin-strap settings. output voltage selection the output voltage may be set to a voltage between 0.6v and 5v if the input voltage is higher th an the desired output voltage by an amount sufficient to maintain regulation. the vset pin is used to set the output voltage to levels as shown in table 3 . the r set resistor is placed between the vset pin and sgnd. a standard 1% resistor is required. the output voltage may also be set to any value between 0.6v and 5v using the pmbus command vout_command. this device supports dynamic voltage scaling by allowing change to the output voltage set point during regulation . the voltage transition rate is specified with the pmbus co mmand vout_transition_rate. by default, v out_max is set 110% higher than v out set by the pin strap resistor, which can be change d to any value up to 5.5v with the pmbus command vout_max. soft-start/stop delay and ramp times the isl8272m follows an internal start-up procedure after power is applied to the vdd pin. the module requires approximately 60ms to 70ms to check for specific values stored in its internal memory and programmed by pin- strap resistors. once this process is completed, the device is ready to accept commands from the pmbus interface and the module is ready to be enabled. if the module is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting the en pin. it may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. in addition, the designer may wish to precisely set the time required for v out to ramp to its target value after the delay period has expired. these features may be used as part of an overall in-rush current management strategy or to precisely control how fast a load ic is turned on. the isl8272m gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start delay and ramp up time can be programmed to custom values with the pmbus commands ton_delay and ton_rise. when the delay time is set to 0ms, the device begins its ramp-up after the internal circuitry has initialized (approximately 2ms). when the soft -start ramp period is set to 0ms, the output ramps up as quickly as the output load capacitance and loop settings allow. it is generally table 3. output voltage resistor settings v out (v) r set (k ) 0.60 10 0.65 11 0.70 12.1 0.75 13.3 0.80 14.7 0.85 16.2 0.90 17.8 0.95 19.6 1.00 21.5, or connect to sgnd 1.05 23.7 1.10 26.1 1.15 28.7 1.20 31.6, or open 1.25 34.8 1.30 38.3 1.40 42.2 1.50 46.4 1.60 51.1 1.70 56.2 1.80 61.9 1.90 68.1 2.00 75 2.10 82.5 2.20 90.9 2.30 100 2.50 110, or connect to v25 2.80 121 3.00 133 3.30 147 4.00 162 5.00 178 table 3. output voltage resistor settings (continued) v out (v) r set (k )
isl8272m fn8670 rev.5.00 page 18 of 59 nov 8, 2017 recommended to set the soft-start ramp to a value greater than 1ms to prevent inadvertent fault conditions due to excessive in-rush current. similar to the soft-start delay and ramp up time, the delay and ramp down time for soft-stop/off can be programmed with the pmbus commands toff_delay and toff_fall. in addition, the module can be configured as ?immediate off? with the command on_off_config, such that the fe ts are turned off immediately after the delay time expires. in current sharing mode where multiple isl8272m modules are connected in parallel, ascr must be disabled for the ramp up with the user_config command. therefore, the soft-start rise time is not equal to ton_rise. it can be calculated approximately by equation 1. in current sharing mode, ascr will be enabled automatically upon power good assertion after the ramp completes. to avoid premature ascr turn on, it is recommended to increase power_good_delay if the rise time exceeds 10ms. in addition, only ?immediate off? is supported for current sharing. the ss/uvlo pin can be used to program the soft start/stop delay time and ramp time to some typical values as shown in table 4 . a standard 1% resistor is required. power-good the isl8272m provides a power-good (pg) signal that indicates the output voltage is within a sp ecified tolerance of its target level and no fault condition exists . by default, the pg pin asserts if the output is within 10% of the target voltage. this limit may be changed using the pmbus command power_good_on. a pg delay period is defined as the time from when all conditions within the isl8272m for asserting pg are met to when the pg pin is actually asserted. this feature is commonly used instead of using an external reset controller to control external digital logic. a pg delay can be programmed with the pmbus command power_good_delay. switching frequency and pll the device?s switching frequency is set from 296khz to 1067khz using the pin strap method (for standalone non-current sharing module only) as shown in table 5 , or by using the pmbus command frequency_switch. the isl8272m incorporates an internal phase-locked loop (pll) to clock the internal circuitry. the pll can be driven by an external clock source connected to the sync pin. the incoming clock signal must be in the range of 300khz to 1.33mhz and must be stable when the enable pin is asserted. when using an external clock, the frequencies are not limited to discrete values as when using the internal clock. the external clock signal must not vary more than 10% from its initial value and should have a minimum pulse width of 150ns. it is recommended that when using an external clock, the same frequency should be set in the frequency_switch command. in case the external clock is lost, the module will automatically switch to the internal clock. when using the internal oscillator, the sync pin can be configured as a clock source as an external sync to other modules. refer to the sync_config command on page 48 for more information. note: if the pin-strap method is used, a standard 1% resistor is required. table 4. soft start/stop resistor settings delay time (ms) ramp time (ms) r set (k ) 5 2 19.6, or connect to sgnd 10 2 21.5 5 5 23.7, or open 10 5 26.1 20 5 28.7 51031.6 10 10 34.8, or connect to v25 20 10 38.3 5 2 42.2 10 2 46.4 5551.1 10 5 56.2 20 5 61.9 5 10 68.1 10 10 75 20 10 82.5 rise time (ms) ton_rise v in f sw ? ------------------------------ - 330khz 12v ? ? ? (eq. 1) table 5. switching frequency resistor settings f sw (khz) r set (k ) 296 14.7, or connect to sgnd 320 16.2 364 17.8 400 19.6 421 21.5, or open 471 23.7 533 26.1 571 28.7 615 31.6, or connect to v25 727 34.8 800 38.3 842 42.2 889 46.4 1067 51.1
isl8272m fn8670 rev.5.00 page 19 of 59 nov 8, 2017 loop compensation the module loop response is programmable using the pmbus command ascr_config or by using the pin-strap method (ascr pin) according to table 6 . a standard 1% resistor is required. the isl8272m uses the chargemo de? control algorithm that responds to output current changes within a single pwm switching cycle, achieving a smaller total output voltage variation with less output capacitance th an traditional pwm controllers. input undervoltage lockout (uvlo) the input undervoltage lockout (uvlo) prevents the isl8272m from operating when the input fa lls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 4.18v and 16v by using a pmbus command vin_uv_fault_limit. using the pin strap method (ss/uvlo pin) as shown in table 7 , allows to set the v uvlo to two typical values. a standard 1% resistor is required. fault response to an input undervoltage fault can be programmed with pmbus command vin_uv_fault_response. if the input undervoltage fault retry is enabled, the module will shut down immediately once the input voltage falls below v uvlo and then check the input voltage every 70ms. if the input voltage rises above the input undervoltage warning level, the module will restart. the input undervoltage warning is 1.05*v uvlo by default and can be programmed with the pmbus command vin_uv_warn_limit. note that fault retry is not supported in the current sharing configuration. smbus module address selection each module must have its own unique serial address to distinguish between other devices on the bus. the module address is set by connecting a resistor between the sa pin and sgnd. table 8 lists the available module addresses. a standard 1% resistor is required. table 6. ascr resistor settings ascr gain ascr residual r set (k ) 80 90 10 120 90 11, or connect to sgnd 160 90 12.1 200 90 13.3, or open 240 90 14.7 280 90 16.2 320 90 17.8 360 90 19.6 400 90 21.5 450 90 23.7 500 90 26.1 550 90 28.7 600 90 31.6 700 90 34.8 800 90 38.3 80 100 42.2 120 100 46.4 160 100 51.1 200 100 56.2 240 100 61.9 280 100 68.1 320 100 75 360 100 82.5 400 100 90.9 450 100 100 500 100 110, or connect to v25 550 100 121 600 100 133 700 100 147 800 100 162 table 7. uvlo resistor settings uvlo (v) r set (k ) 4.5 open 4.5 connect to v25 4.5 connect to sgnd 4.5 19.6, 21.5, 23.7, 26.1, 28.7, 31.6, 34.8, 38.3 10.8 42.2, 46.4, 51.1, 56.2, 61.9, 68.1, 75, 82.5, table 8. smbus address resistor selection r sa (k )smbus address 10 19h 11 1ah 12.1 1bh 13.3 1ch 14.7 1dh 16.2 1eh 17.8 1fh 19.6 20h 21.5 21h 23.7 22h 26.1 23h 28.7 24h 31.6 25h 34.8, or connect to sgnd 26h 38.3 27h 42.2, or open 28h 46.4 29h 51.1 2ah 56.2 2bh 61.9 2ch 68.1 2dh 75 2eh
isl8272m fn8670 rev.5.00 page 20 of 59 nov 8, 2017 output overvoltage protection the isl8272m offers an internal output overvoltage protection circuit that can protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. a hardware comparator compares th e actual output voltage (seen at the vsenp and vsenn pins) to a threshold set to 15% higher than the target output voltage (the default setting). the fault threshold can be programmed to a desired level with the pmbus command vout_ov_fault_limit. if the vsenp voltage exceeds this threshold, the module will initiate an immediate shutdown without retry. a 70ms continuous retry can be enabled with the pmbus command vout_ov_fault_response. note that fault retry is not supported in the current sharing configuration. internal to the module, two 22 resistors are populated from v out to vsenp and sgnd to vsenn to protect from overvoltage conditions in case of open at voltage sensing pins and differential remote sense traces due to assembly error. as long as differential remote sense traces have low resistance, v out regulation accuracy is not sacrificed. output prebias protection an output prebias condition exis ts when an externally applied voltage is present on a power supply?s output before the power supply?s control ic is enabled. certain applications require that the converter not be allowed to si nk current during start-up if a prebias condition exists at the output. the isl8272m provides prebias protection by sampling the output voltage prior to initiating an output ramp. if a prebias voltage lower than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing prebias voltage and both drivers are enabled. the output voltage is then ramped to the final regulation value at the pre-configured ramp rate. the actual time the output takes to ramp from the prebias voltage to the target voltage varies, depending on the prebias voltage; however, the total time elapsed from when the delay period expires to when the output reaches its target value will match the pre-configur ed ramp time (see figure 26 ). if a prebias voltage is higher than the target voltage after the pre- configured delay period has expired, the target voltage is set to match the existing prebias voltage and both drivers are enabled with a pwm duty cycle that would ideally create the prebias voltage. once the preconfigured soft-start ramp period has expired, the pg pin is asserted (assuming the prebias voltage is not higher than the overvoltage limit). the pwm then adjusts its duty cycle to match the original target voltage and the output ramps down to the pre-configured output voltage. if a prebias voltage is higher than the overvoltage limit, the device does not initiate a turn-on sequence and declares an overvoltage fault condition. the device then responds based on the output overvoltage fault resp onse setting programmed with the pmbus command vout_ov_fault_response. output overcurrent protection the isl8272m can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. average output overcurrent fault threshold can be programmed with the pmbus command iout_oc_fault_limit. the module automatically programs the peak inductor current fault threshold by calculating the inductor ripple current from the input voltage, switching frequency, and the vout_command. when the peak inductor current crosses the peak inductor current fault threshold for three su ccessive switching cycles it will initiate an immediate shutdown. the default response from an ov ercurrent fault is an immediate shutdown without retry. a 70ms continuous retry can be enabled with the pmbus command mfr_ iout_oc_fault_response. it is required to enable the output undervoltage fault retry with the pmbus command vout_uv_fault_response command simultaneously if the overcurrent fault retry is enabled. note that fault retry is not supported in the current sharing configuration. 82.5 2fh 90.9 30h 100 31h 110 32h 121 33h 133 34h 147 35h 162 36h 178 37h table 8. smbus address resistor selection (continued) r sa (k )smbus address figure 26. output responses to prebias voltages desired output voltage prebias voltage v out time ton- delay ton- rise desired output voltage prebias voltage v out time v prebias < v target v prebias > v target ton- rise ton- delay
isl8272m fn8670 rev.5.00 page 21 of 59 nov 8, 2017 thermal overload protection the isl8272m includes a therma l sensor that continuously measures the internal temperat ure of the module and shuts down the controller when the temperature exceeds the preset limit. the default temperature limit is set to +125c in the factory, but can be changed with pmbus command ot_fault_limit. the default response from an over-temperature fault is an immediate shutdown without retry. retry settings can be programmed with the pmbus command ot_fault_response. hysteresis is implemented with the over-temperature fault retry. if retry is enabled, the module will shut down immediately upon an over-temperature fault event and then check the temperature every 70ms. if the temperature falls below the over-temperature warning level, the module will restart. the over-temperature warning is +105by default and programmable with the pmbus command ot_warn_limit. note that fault retry is not supported in the current sharing configuration. digital-dc bus the digital-dc communications (ddc) bus is used to communicate between intersil digital power modules and digital controllers. this dedicated bu s provides the communication channel between devices for featur es such as current sharing, sequencing, and fault spreading. the ddc pin on all digital-dc devices in an application should be connected together. a pull-up resistor is required on the ddc bu s in order to guarantee the rise time as shown in equation 2 : where r pu is the ddc bus pull-up resistance and c load is the bus loading. the pull-up resistor may be tied to an external 3.3v or 5v supply as long as this voltage is present prior to or during device power-up. in principle, each device connected to the ddc bus presents approximately 10pf of capacitive loading and each inch of fr4 pcb trace introduces approximately 2pf. the ideal design uses a central pull-up resistor that is well-matched to the total load capacitance. active current sharing paralleling multiple isl8272m modules can increase the output current capability of a single po wer rail. by connecting the ddc and sync pins of each module together and configuring the modules as a current sharing rail, the units will share the current equally within a few percent. figure 27 illustrates a typical connection for two modules. the isl8272m uses a ddc bus based digital current sharing technique to balance the steady state module output current by aligning the load lines of me mber modules to a reference module. when multiple isl8272m modules are connected for current sharing, a non-zero active droop resistance must be set to add artificial resistance in the output voltage path to control the slope of the load line curve, calibrating out the physical parasitic mismatches due to power train components and pcb layout. the active droop resistance can be programmed with the pmbus command vout_droop based on equation 3 . typically, higher droop value offers a more accura te dynamic current sharing at the sacrifice of output load regulation. 1% droop at full load will be a good trade-off between outp ut load regulation and dynamic current sharing. upon system start-up, the module with the lowest device position as selected in ddc_config is defined as the reference module. the remaining modules are members. the reference module broadcasts its current over the ddc bus. the members use the reference current information to trim their voltages (v member ) to balance the current loading of each module in the system. rise time r pu ? c load 1 ? s ? = (eq. 2) isl8272m v out isl8272m v in c out c in c out c in ddc ddc 3.3v to 5v sync sync figure 27. current sharing group v out i load max ?? --------------------------------- - 0.005 ? droop v out i load max ?? --------------------------------- - 0.01 ? 5 ?? (eq. 3) -r -r v reference v member i member i reference i out v out figure 28. active current sharing
isl8272m fn8670 rev.5.00 page 22 of 59 nov 8, 2017 figure 28 on page 21 shows that, for load lines with identical slopes, the member voltage is increased towards the reference voltage which closes the gap between the inductor currents. the relation between reference and member current and voltage is given by equation 4 : where r is the value of the droop resistance. the ddc_config command configures the module for active current sharing. the default setting is a standalone non current sharing module. for fault configuration, it is required to enable the fault spreading mode in the current sharing rail with the pmbus command ddc_group. broadcast operation must be enabled with the ddc_group command to allow start up/shut down and margining operations. it is optional to enable v out broadcast in the ddc_group command to allow v out set point change dynamically during operation. in the multiple-module current sharing configuration, it is required to synchronize all modules to the same switching clock by tying the sync pins together. the clock source can be selected either from one module or from an external clock with the sync_config command. the phase offset of current sharing modules is automatically set according to the device positions and number of devices specified in the ddc_config command. the pin strap method is offered for the current sharing configuration with the cs pin. table 9 lists the current sharing pin strap settings. a standard 1% resist or is required. note that fault retry is not supported in the current sharing configuration. phase spreading when multiple point-of-load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device so that not all devices start to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. because the peak current drawn from the input supply is effectively spread out over a period of time, the peak curren t drawn at any given moment is reduced and the power losses proportional to the i rms 2 are reduced dramatically. to enable phase spreading, all co nverters must be synchronized to the same switching clock. the phase offset of each device may also be set to any value between 0 and 360 in 22.5 increments with the pmbus command interleave. the internal two phases of the module always maintain a phase difference of 180. fault spreading digital-dc modules and devices can be configured to broadcast a fault event over the ddc bus to the other devices in the group with the pmbus command ddc_gr oup. when a nondestructive fault occurs, the device shuts down and broadcasts the fault table 9. current sharin g resistor settings clock configuration device position - number of devices droop (mv/a) r set (k ) output internal 1-2 0.1 10 external 2-2 0.1 11 output internal 1-2 0.15 12.1 external 2-2 0.15 13.3 output internal 1-2 0.2 14.7 external 2-2 0.2 16.2 output internal 1-2 0.25 17.8 external 2-2 0.25 19.6 output internal 1-2 0.3 21.5 external 2-2 0.3 23.7 output internal 1-3 0.07 26.1 external 2-3 0.07 28.7 external 3-3 0.07 31.6 output internal 1-3 0.1 34.8 external 2-3 0.1 38.3 external 3-3 0.1 42.2 (eq. 4) v member v out ri reference i member C ?? ? + = )
isl8272m fn8670 rev.5.00 page 23 of 59 nov 8, 2017 event over the ddc bus. the other devices on the ddc bus shut down simultaneously if configured to do so, and attempt to restart. note that fault retry is not supported in multiple modules with fault spreading enabled, such as the current sharing configuration. output sequencing a group of digital-dc modules or devices may be configured to power-up in a predetermined sequence. this feature is especially useful when powering advanced processors (fpgas and asics) that require one supply to reac h its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up. multi-device sequencing can be achieved by configuring each device with the pmbus command sequence. multiple device sequencing is configured by issuing pmbus commands to assign the preceding device in the sequencing chain as well as the device that follows in the sequencing. the enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. enable must be driven lo w to initiate a sequenced turnoff of the group. it is recommend to enable fault spreading with the pmbus command ddc_group within a sequencing group. monitoring with smbus a system controller can monito r a wide variety of different isl8272m system parameters with pmbus commands: ?read_vin ?read_vout ?read_iout ? read_internal_temp ? read_duty_cycle ? read_freqeuncy ?read_vmon snapshot parameter capture the isl8272m offers a special feature to capture parametric data and some fault status following a fault. a detailed description is provided in ? pmbus commands description ? on page 29 under the pmbus commands snapshot and snapshot_control. nonvolatile memory the isl8272m has internal nonvolatile memory where user configurations are stored. integr ated security measures ensure that the user can only restore the module to a level that has been made available to them. during the initialization process, the isl8272m checks for stored values contained in its internal nonvolatile memory. modules are shipped with a factory default configuration and most settings can be overwritten with pmbus commands and can be stored in nonvolatile memory with the pmbus command store_user_all. layout guide to achieve stable operation, low losses, and good thermal performance, proper layout ( figure 29 ) is important. ? establish separate sgnd plane and pgnd planes, then connect sgnd to the pgnd plane on the middle layer and underneath pad6 with a single point connection. for sgnd and pgnd pin connections, such as small pins h16, j16, m5, and m17..., use multiple vias for each pin to connect to the inner sgnd or pgnd layer. ? place enough ceramic capacitors between vin and pgnd, vout and pgnd and bypass capacitors between vdd, vdrv and the ground plane, as close to the module as possible to minimize high frequency noise. it is critical to place the output ceramic capacitors as close to the center of the two vout pads as possible, to create a low impedance path for the high frequency inductor ripple current. ? use large copper areas for power path (vin, pgnd, vout) to minimize conduction loss and thermal stress. also, use multiple vias to connect the power planes in different layers. it is recommended to enlarge pad11 and pad15 and to put more vias on these pads. the ceramic caps cin can be put on the bottom layer under these two pads. ? connect remote sensed traces to the regulation points to achieve a tight output voltage regulation and keep them in parallel. route a trace from vsenn and vsenp to the point of load where the tight output volt age is desired. avoid routing any sensitive signal traces, such as the vsenn, vsenp sensing point near the sw pins. ? the sw1 and sw2 pads are noisy pads, but they are beneficial for thermal dissipations. if the noise issue is critical for the applications, it is recommended to use top layer only for sw pads. for better thermal performance, use multiple vias on these pads to connect into sw inner and bottom layer. however, be very careful when placing limited sw planes in any layer. the sw planes should avoid the sensing signals and should be surrounded by the pgnd layer to avoid noise coupling. ? for pins swd1 (l3) and swd2 (p10), it is recommended to connect to the related sw1 and sw2 pads with short loop wires. the wire width should be greater than 20 mils.
isl8272m fn8670 rev.5.00 page 24 of 59 nov 8, 2017 thermal considerations experimental power loss curves along with ja from thermal modeling analysis can be used to evaluate the thermal consideration for the module. the derating curves are derived from the maximum power allowed while maintaining the temperature below the maximum junction temperature of +125c. in actual applications, other heat sources and design margins should be considered. package description the structure of the isl8272m belongs to the high density array no-lead package (hda). this package offers good thermal and electrical conductivity, low weight, and small size. the hda package is applicable for surfac e mounting technology and is being more readily used in the industry. the isl8272m contains several types of devices, incl uding resistors, capacitors, inductors, and control ics. the isl8272m is a copper lead-frame based package with exposed copper thermal pads, which have good electrical and thermal conductivity. the copper lead frame and multi component assembly is overmolded with polymer mold compound to protect these devices. the package outline and typical pcb layout pattern design and typical stencil pattern design are shown in the ? package outline drawing ? starting on page 53 . the module has a small size of 18mmx23mmx7.5mm. pcb layout pattern design the bottom of the isl8272m is a lead-frame footprint, which is attached to the pcb by a surface mounting process. the pcb layout pattern is shown on pages 57 to 59 . the pcb layout pattern is an array of solder ma sk defined pcb lands which align with the perimeters of the hda exposed pads and i/o termination dimensions. the thermal lands on the pcb layout also feature an array of solder mask defined lands and should match 1:1 with the package exposed die pad perimeters. the exposed solder mask defined pcb land area should be 50-80% of the available module i/o area. thermal vias a grid of 1.0mm to 1.2mm pitch thermal vias, which drops down and connects to buried copper plan e(s), should be placed under the thermal land. the vias should be about 0.3mm to 0.33mm in diameter with the barrel plated to about 1.0 ounce copper. although adding more vias (by decreasing via pitch) will improve the thermal performance, diminishin g returns will be seen as more and more vias are added. simply use as many vias as practical for the thermal land size and your board design rules allow. stencil pattern design reflowed solder joints on the perimeter i/o lands should have about a 50m to 75m (2mil to 3m il) standoff height. the solder paste stencil design is the first step in developing optimized, reliable solder joints. the stencil aperture size to solder mask defined pcb land size ratio should typically be 1:1. the aperture width may be reduced slightly to help prevent solder bridging between adjacent i/o lands. a typical solder stencil pattern is shown in the ? package outline drawing ? starting on page 55 . the gap width between pad to pad is 0.6mm. consider the symmetry of the whole stencil pattern when designing its pads. a laser cut, stainless steel stencil with electropolished trapezoidal walls is recommended. electropolishing ?smooths? the aperture walls, resulting in reduced surface friction and better paste release which reduces voids. using a trapezoida l section aperture (tsa) also promotes paste release and forms a brick-like paste deposit that assists in firm component placem ent. a 0.1mm to 0.15mm stencil thickness is recommended for this large pitch hda. reflow parameters due to the hda?s low mount height, ?no clean? type 3 solder paste per ansi/j-std-005 is re commended. nitrogen purge is recommended during reflow. a system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the hda. the profile in figure 30 is a guideline to be customized for varying manufacturing practices and applications. figure 29. recommended layout pgnd vin vin pgnd pgnd vout sgnd vsen+ vsen- kelvin connections cin cin pgnd pgnd cout cout 0300 100 150 200 250 350 0 50 100 150 200 250 300 temperature (c) duration (s) slow ramp (3c/s max) and soak from +150c to +200c for 60s~180s ramp rate ? 1.5c from +70c to +90c peak temperature ~+245c; typically 60s-150s above +217c keep less than 30s within 5c of peak temp.
isl8272m fn8670 rev.5.00 page 25 of 59 nov 8, 2017 pmbus command summary command code command name description type data format default value default setting page 01h operation sets enable, disable and v out margin modes. r/w byte bit 29 02h on_off_config configures the en pin and pmbus commands to turn the unit on/off r/w byte bit 16h hardware enable, soft off 29 03h clear_faults clears fault indications. send byte 30 15h store_user_all stores all pmbus values written since last restore at user level. send byte 30 16h restore_user_all restores pmbus settings that were stored using store_user_all. send byte 30 20h vout_mode preset to defined data format of v out commands. read byte bit 13h linear mode, exponent = -13 30 21h vout_command sets the nominal value of the output voltage. r/w word l16u pin strap 30 23h vout_cal_offset applies a fixed offset voltage to the vout_command. r/w word l16s 0000h 0v 31 24h vout_max sets the maximum possible value of v out . 110% of pin strap v out . r/w word l16u 1.1*v out pin strap 31 25h vout_margin_high sets the value of the v out during a margin high. r/w word l16u 1.05*v out pin strap 31 26h vout_margin_low sets the value of the v out during a margin low. r/w word l16u 0.95*v out pin strap 31 27h vout_transition_rate sets th e transition rate during margin or other change of v out . r/w word l11 ba00h 1v/ms 31 28h vout_droop sets the loadline (v/i slope) resistance for the rail. r/w word l11 pin strap 32 33h frequency_switch sets the switching frequency. r/w word l11 pin strap 32 37h interleave configures a phase offset between devices sharing a sync clock. r/w word bit 0000h 32 38h iout_cal_gain sense resistance for inductor dcr current sensing. r/w word l11 b370h 0.86m 32 39h iout_cal_offset sets the current-sense offset. r/w word l11 0000h 0a 32 40h vout_ov_fault_limit sets the v out overvoltage fault threshold. r/w word l16u 1.15*v out pin strap 33 41h vout_ov_fault_response configures the v out overvoltage fault response. r/w byte bit 80h disable and no retry 33 42h vout_ov_warn_limit sets the v out overvoltage warn threshold. r/w word l16u 1.10*v out pin strap 33 43h vout_uv_warn_limit sets the v out undervoltage warn threshold. r/w word l16u 0.9 * v out pin strap 33 44h vout_uv_fault_limit sets the v out undervoltage fault threshold. r/w word l16u 0.85*v out pin strap 33 45h vout_uv_fault_response configures the v out undervoltage fault response. r/w byte bit 80h disable and no retry 34 46h iout_oc_fault_limit sets the i out average overcurrent fault threshold. r/w word l11 e3c0h 60a 34 4bh iout_uc_fault_limit sets the i out average undercurrent fault threshold. r/w word l11 e440h -60a 34 4fh ot_fault_limit sets the over-temperature fault threshold. r/w word l11 ebe8h +125c 34 50h ot_fault_response configures the over-temperature fault response. r/w byte bit 80h disable and no retry 35
isl8272m fn8670 rev.5.00 page 26 of 59 nov 8, 2017 51h ot_warn_limit sets the over-temperature warning limit. r/w word l11 eb48h +105c 35 52h ut_warn_limit sets the under-temperature warning limit. r/w word l11 dc40h -30c 35 53h ut_fault_limit sets the under-temperature fault threshold. r/w word l11 e580h -40c 35 54h ut_fault_response configures the under-temperature fault response. r/w byte bit 80h disable and no retry 36 55h vin_ov_fault_limit sets the v in overvoltage fault threshold. r/w word l11 d380h 14v 36 56h vin_ov_fault_response configures the v in overvoltage fault response. r/w byte bit 80h disable and no retry 36 57h vin_ov_warn_limit sets the input overvoltage warning limit. r/w word l11 d353h 13.3v 36 58h vin_uv_warn_limit sets the input undervoltage warning limit. r/w word l11 1.05*v in uv fault limit 37 59h vin_uv_fault_limit sets the v in undervoltage fault threshold. r/w word l11 pin strap 37 5ah vin_uv_fault_response configures the v in undervoltage fault response. r/w byte bit 80h disable and no retry 37 5eh power_good_on sets the voltage threshold for power-good indication. r/w word l16u 0.9*v out pin strap 37 60h ton_delay sets the delay time from enable to start of v out rise. r/w word l11 pin strap 37 61h ton_rise sets the rise time of v out after enable and ton_delay. r/w word l11 pin strap 38 64h toff_delay sets the delay time from disable to start of v out fall. r/w word l11 pin strap 38 65h toff_fall sets the fall time for v out after disable and toff_delay. r/w word l11 pin strap 38 78h status_byte returns an abbreviated status for fast reads. read byte bit 00h no faults 38 79h status_word returns information with a summary of the units's fault condition. read word bit 0000h no faults 39 7ah status_vout returns the v out specific status. read byte bit 00h no faults 39 7bh status_iout returns the i out specific status. read byte bit 00h no faults 40 7ch status_input returns specific status specific to the input. read byte bit 00h no faults 40 7dh status_temperature returns the temperature specific status. read byte bit 00h no faults 40 7eh status_cml returns the communication, logic and memory specific status. read byte bit 00h no faults 41 80h status_mfr_specific returns the vmon and external sync clock specific status. read byte bit 00h no faults 41 88h read_vin returns the input voltage reading. read word l11 41 8bh read_vout returns the output voltage reading. read word l16u 41 8ch read_iout returns the output current reading. read word l11 42 8dh read_internal_temp returns the temperature reading internal to the device. read word l11 42 pmbus command summary (continued) command code command name description type data format default value default setting page
isl8272m fn8670 rev.5.00 page 27 of 59 nov 8, 2017 94h read_duty_cycle returns the duty cycle reading during the enable state. read word l11 42 95h read_frequency returns the measured operating switch frequency. read word l11 42 96h read_iout_0 returns phase 1 current reading. read word l11 42 97h read_iout_1 returns phase 2 current reading. read word l11 42 99h mfr_id sets a user defined identification. r/w block asc null 43 9ah mfr_model sets a user defined model. r/w block asc null 43 9bh mfr_revision sets a user defined revision. r/w block asc null 43 9ch mfr_location sets a user defined location identifier. r/w block asc null 43 9dh mfr_date sets a user defined date. r/w block asc null 43 9eh mfr_serial sets a user defined serialized identifier. r/w block asc null 44 a8h legacy_fault_group sets rail ids of legacy devices for fault spreading r/w block bit 00000000h no rail id specified 44 b0h user_data_00 sets a user defined data. r/w block asc null 44 d0h isense_config configures isense related features. r/w byte bit 05h 256ns blanking time, mid range 44 d1h user_config configures several user-level features. r/w byte bit pin strap (ascr on/off for start up) 45 d3h ddc_config configures the ddc bus. r/w word bit pin strap (set based on pmbus address and cs) 45 d4h power_good_delay sets the delay between v out > pg threshold and asserting the pg pin. r/w word l11 c300h 3ms 46 dfh ascr_config configures ascr co ntrol loop. r/w block cus pin strap 46 e0h sequence identifies the rail ddc id to perform multi-rail sequencing. r/w word bit 0000h prequel and sequel disabled 46 e2h ddc_group sets rail ddc ids to obey faults and margining spreading information. r/w block bit pin strap (set based on cs) 47 e4h device_id returns the 16-byte (character) device identifier string. read block asc reads device version 47 e5h mfr_iout_oc_fault_response configures the i out overcurrent fault response. r/w byte bit 80h disable and no retry 47 e6h mfr_iout_uc_fault_response configures the i out undercurrent fault response. r/w byte bit 80h disable and no retry 48 e9h sync_config configures the sync pin. r/w byte bit pin strap (set based on cs) 48 eah snapshot returns 32-byte read-back of parametric and status values. read block bit 49 ebh blank_params returns recently changed parameter values. read block bit ff...ffh 49 f3h snapshot_control snapshot feature control command. r/w byte bit 49 f4h restore_factory restores device to the factory default values. send byte 50 f5h mfr_vmon_ov_fault_limit returns the vmon overvoltage threshold. read word l11 cb00h 6v 50 pmbus command summary (continued) command code command name description type data format default value default setting page
isl8272m fn8670 rev.5.00 page 28 of 59 nov 8, 2017 pmbus data formats linear-11 (l11) the l11 data format uses 5-bit two?s complement exponent (n) an d 11-bit two?s complement mantissa (y) to represent real world decimal value (x). the relation between real world decimal value (x), n and y is: x = y2 n linear-16 unsigned (l16u) l16u data format uses a fixed exponent (hard-coded to n = -13h) and a 16-bit unsigned integer mantissa (y) to represent real wo rld decimal value (x). relation between real world decimal value (x), n and y is: x = y2 -13 linear-16 signed (l16s) the l16s data format uses a fixed exponent (hard-coded to n = - 13h) and a 16-bit two?s complement mantissa (y) to represent rea l world decimal value (x). relation between real world decimal value (x), n and y is: x = y2 -13 bit field (bit) an explanation of bit field is provided in ? pmbus commands description ? on page 29 . custom (cus) an explanation of custom data format is provided in ? pmbus commands description ? on page 29 . a combination of bit field and integer are common type of custom data format. ascii (asc) a variable length string of text charac ters that uses the ascii data format. f6h mfr_vmon_uv_fault_limit returns the vmon undervoltage threshold. read word l11 ca00h 4v 50 f7h mfr_read_vmon returns the vmon voltage reading. read word l11 50 f8h vmon_ov_fault_response returns the vmon overvoltage response. read byte bit 80h disable and no retry 50 f9h vmon_uv_fault_response returns the vmon undervoltage response. read byte bit 80h disable and no retry 50 pmbus command summary (continued) command code command name description type data format default value default setting page data byte high data byte low exponent (n) mantissa (y) 76543210 76543210
isl8272m fn8670 rev.5.00 page 29 of 59 nov 8, 2017 pmbus use guidelines the pmbus is a powerful tool that allows the user to optimize circuit performance by configuring devices for their application. when configuring a device in a circuit, the device should be disabl ed whenever most settings are ch anged with pmbus commands. some exceptions to this recommendation are operation, on_off_config, clear_faults, vout_command, vout_margin_high, vout_margin_low, and asccr_config. while the device is enabled any command can be read. many commands do not take effect until after the device has been re-enabled, hence the recommendati on that commands that change device settings are written whil e the device is disabled. when sending the store_default_all, store_user_all, rest ore_default_all, and restor e_user_all commands, it is recommended that no other commands ar e sent to the device for 100ms afte r sending store or restore commands. in addition, there should be a 2ms delay between repeated read commands sent to the same device. when sending any other command, a 5ms delay is recommended between repeated commands sent to the same device. comm ands not listed in the pmbus command summary are not allowed for customer use, and are reserv ed for factory use only. issuing reserved commands may result i n unexpected operation. summary all commands can be read at any time. always disable the device when writing comman ds that change device settings. exceptions to this rule are commands intended to b e written while the device is enabled, for example, vout_margin_high. to be sure a change to a device setting has taken effect, writ e the store_user_all command, then cycle input power and re-enabl e. pmbus commands description operation (01h) definition: sets enable, disable, and v out margin settings. operation data values that fo rce the margin high or low only take effect when the mgn pin is left open (in the nominal margin state). data length in bytes : 1 data forma t: bit type : r/w default value : units : n/a on_off_config (02h) definition: configures the interpretation and coordination of the operation command and the enable pin (en). data length in bytes : 1 data format : bit type : r/w default value : 16h (device starts from enable pin with soft off) units : n/a settings actions 04h immediate off (no sequencing) 44h soft off (with sequencing) 84h on - nominal 94h on - margin low a4h on - margin high settings actions 16h device starts from enable pin with soft off. 17h device starts from enable pin with immediate off. 1ah device starts from operation command with soft off. 1bh device starts from operation command with immediate off.
isl8272m fn8670 rev.5.00 page 30 of 59 nov 8, 2017 clear_faults (03h) definition : clears all fault bits in all registers and releases the salr t pin (if asserted) simultaneously. if a fault condition still ex ists, the bit will reassert immediately. this command will not restart a device if it has shut down, it will only clear the faults. data length in bytes : 0 byte data format : n/a type : write only default valu e: n/a units : n/a reference: n/a store_user_all (15h) definition : stores all pmbus settings from the operating memory to the nonvolatile user store memory. to clear the user store, perform a restore_factory then store_user_all. to add to the user store, perform a restore_user_all, write commands to be added, then store_user_all. this command can be used during device operation, but the device will be unresponsive for 20ms while storing values. data length in bytes : 0 data format : n/a type : write only default value : n/a units: n/a restore_user_all (16h) definition: restores all pmbus settings from the user store memory to the operating memory. command performed at power-up. security level is changed to level 1 following this command. this command can be used during device operation, but the device w ill be unresponsive for 20ms while storing values. data length in bytes: 0 data format: n/a type: write only default value: n/a units: n/a vout_mode (20h) definition: reports the v out mode and provides the exponent used in calculating several v out settings. fixed with linear mode with default exponent (n) = -13 data length in bytes: 1 data format: bit type: read-only default value: 13h (linear mode, n = -13) units: n/a vout_command (21h) definition: sets or reports the target output voltage. this command canno t set a value higher than either vout_max or 110% of the pin strap v out setting. data length in bytes: 2 data format: l16u type: r/w default value: pin strap setting units: volts range: 0v to vout_max
isl8272m fn8670 rev.5.00 page 31 of 59 nov 8, 2017 vout_cal_offset (23h) definition: applies a fixed offset voltage to the output voltage command value. this command is typically used by the user to calibrate a device in the application circuit. data length in bytes: 2 data format: l16s type: r/w default value: 0000h units: volts vout_max (24h) definition: sets an upper limit on the output voltage the unit can co mmand regardless of any other commands or combinations. the intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructi ve level rather than to be the primary output overprotecti on. the default value can be changed using pmbus. data length in bytes: 2 data format: l16u type: r/w default value: 1.10xvout_command pin strap setting units: volts range: 0v to 5.5v vout_margin_high (25h) definition: sets the value of the v out during a margin high. the vout_margin_high co mmand loads the unit with the voltage to which the output is to be changed when the operatio n command or mgn pin is set to ?margin high?. data length in bytes: 2 data format: l16u type: r/w default value: 1.05 x vout_command pin strap setting units: v range: 0v to vout_max vout_margin_low (26h) definition: sets the value of the v out during a margin low. the vout_margin_low comm and loads the unit with the voltage to which the output is to be changed when the operatio n command or mgn pin is set to ?margin low?. data length in bytes: 2 data format: l16u type: r/w default value: 0.95 x vout_command pin strap setting units: v range: 0v to vout_max vout_transition_rate (27h) definition: sets the rate at which the output should change voltage when the device receives the vout_command or an operation command (margin high, margin low) that causes the output voltage to change. the maximum possible positive value of the two data bytes indicates that the device should ma ke the transition as quickly as possible. data length in bytes: 2 data format: l11 type: r/w default value: ba00h (1.0 v/ms) units : v/ms range: 0.1 to 4v/ms
isl8272m fn8670 rev.5.00 page 32 of 59 nov 8, 2017 vout_droop (28h) definition: sets the effective load line (v/i slope) for the rail in which the device is used. it is the rate, in mv/a, at which the outpu t voltage decreases (or increa ses) with increasing (or decreasi ng) output current for use with ad aptive voltage positioning schem es or multi-module current sharing. in the curren t sharing configuration, vout_droop set in each module stands for the droop seen by the load. data length in bytes: 2 data format: l11 type: r/w default value: pin strap setting units: mv/a range: 0 to 40mv/a frequency_switch (33h) definition: sets the switching frequency of the device. the initial default va lue is defined by a pin strap and this value can be overridde n by writing this command using pmbus. if an external sync is ut ilized, this value should be set as close as possible to the exte rnal clock value. the output must be disa bled when writing this command. data length in bytes: 2 data format: l11 type: r/w default value: pin strap setting units: khz range: 300khz to 1066khz interleave (37h) definition: configures the phase offset of a device that is sharing a common sync clock with other devices. the phase offset of each device can be set to any value between 0 and 360 in 22.5 increm ents. the internal two phases of the module always maintain a phase difference of 180. data length in bytes: 2 data format: bit type: r/w default value: 0000h units: n/a iout_cal_gain (38h) definition: sets the effective impedance across the current sense ci rcuit for use in calculating output current at +25c. data length in bytes: 2 data format: l11 type : r/w default value: b370h (0.86m ) units: m iout_cal_offset (39h) definition: used to null out any offsets in the output current sensing ci rcuit and to compensate for delayed measurements of current ramp due to isense blanking time. data length in bytes: 2 data format: l11 type : r/w default value: 0000h (0a) units: a bits purpose value description 15:4 reserved 0 reserved 3:0 position in group 0 to 15 sets position of the device's rail within the group.
isl8272m fn8670 rev.5.00 page 33 of 59 nov 8, 2017 vout_ov_fault_limit (40h) definition: sets the v out overvoltage fault threshold. data length in bytes: 2 data format: l16u type: r/w default value: 1.15xvout_command pin strap setting units: v range: 0v to vout_max vout_ov_fault_response (41h) definition: configures the v out overvoltage fault response. note that the devi ce cannot be set to ignore this fault mode. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a vout_ov_warn_limit (42h) definition: sets the v out overvoltage warning threshold. the power-good signal is pulled low when output voltage goes higher than this threshold. data length in bytes : 2 data format: l16u type: r/w default value: 1.10xvout_command pin strap setting units: v range: 0v to vout_max vout_uv_warn_limit (43h) definition: sets the v out undervoltage warning threshold. the power-good signal is pulled low when output voltage goes lower than this threshold. data length in bytes: 2 data format: l16u type: r/w default value: 0.90xvout_command pin strap setting units: v range: 0v to vout_max vout_uv_fault_limit (44h) definition: sets the v out undervoltage fault threshold. this fault is masked during ramp or when disabled. data length in bytes: 2 data format: l16u type: r/w default value: 0.85xvout_command pin strap setting units: v range: 0v to vout_max settings actions 80h disable with no retry. bfh disable and continuous retry with 70ms delay.
isl8272m fn8670 rev.5.00 page 34 of 59 nov 8, 2017 vout_uv_fault_response (45h) definition: configures the v out undervoltage fault response. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable, no retry) units: n/a iout_oc_fault_limit (46h) definition: sets the i out average overcurrent fault threshold. the device will au tomatically calculate the peak inductor overcurrent fault limit for each phase based on the equation: i out(peak oc limit) = (0.5*iout_oc_fault_limit+0.5*i ripple(p-p) )*120%. a hard bound of 42a is applied to the peak overcurrent fault limit per phase. data length in bytes: 2 data format: l11 type: r/w default value: e3c0h (60a) units: a range: -100 to 100a iout_uc_fault_limit (4bh) definition: sets the i out average undercurrent fault threshold. the device will automatically calculate the va lley inductor undercurrent fault limit for each phase based on the equation: i out(valley uc limit) = (0.5*iout_uc_fault_limit-0.5*i ripple(p-p) )*120%. a hard bound of -42a is applied to the vall ey undercurrent fault limit per phase. data length in bytes: 2 data format: l11 type: r/w default value: -1xiout_oc_fault_limit units: a range: -100 to 100a ot_fault_limit (4fh) definition: sets the temperature at which the device should indicate an over-temperature fault. note that the temperature must drop below ot_warn_limit to clear this fault. data length in bytes: 2 data format: l11 type: r/w default value: ebe8h (+125 ? c) units: celsius range: 0 c to +175 c settings actions 80h disable with no retry. bfh disable and continuous retry with 70ms delay.
isl8272m fn8670 rev.5.00 page 35 of 59 nov 8, 2017 ot_fault_response (50h) definition: instructs the device on what action to take in response to an over-temperature fault. data length in bytes: 1 data format: bit type : r/w fault value: 80h (disable and no retry) units: n/a ot_warn_limit (51h) definition: sets the temperature at which the device should indicate an over-temperature warning alarm. in response to the ot_warn_limit being exceeded, the device sets the temper ature bit in status_word, sets the ot_warning bit in status_temperature, and notifies the host. data length in bytes: 2 data format: l11 type : r/w default value: eb48h (+105c) units: celsius range : 0c to +175c ut_warn_limit (52h) definition: sets the temperature at which the device should indicate an under-temperature warning alarm. in response to the ut_warn_limit being exceeded, the device sets the temper ature bit in status_word, sets the ut_warning bit in status_temperature, and notifies the host. data length in bytes: 2 data format: l11 type : r/w default value: dc40h (-30c) units: celsius range : -55c to +25c ut_fault_limit (53h) definition: sets the temperature, in degrees celsius, of the unit where it should indicate an under-temperature fault. note that the temperature must rise above ut_w arn_limit to clear this fault. data length in bytes: 2 data format: l11 type: r/w default value: e580h (-40c) units: celsius range: -55c to +25c settings actions 80h disable with no retry. bfh disable and continuous retry with 70ms delay.
isl8272m fn8670 rev.5.00 page 36 of 59 nov 8, 2017 ut_fault_response (54h) definition: configures the under-temperature fault response as defined by the following table. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable, no retry) units: n/a vin_ov_fault_limit (55h) definition: sets the v in overvoltage fault threshold. data length in bytes: 2 data format: l11 type: r/w default value: d380h (14v) units: v range: 0v to 16v vin_ov_fault_response (56h) definition: configures the v in overvoltage fault response as defined by the followin g table. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a vin_ov_warn_limit (57h) definition: sets the v in overvoltage warning threshold. in response to the ov _warn_limit being exceeded, the device sets the none of the above and input bits in status_word, sets the vi n_ov_warning bit in status_input, and notifies the host. data length in bytes: 2 data format: l11 type : r/w protectable: yes default value: d353h (13.3v) units: v range : 0v to 16v settings actions 80h disable with no retry. bfh disable and continuous retry with 70ms delay. settings actions 80h disable with no retry. bfh disable and continuous retry with 70ms delay.
isl8272m fn8670 rev.5.00 page 37 of 59 nov 8, 2017 vin_uv_warn_limit (58h) definition: sets the v in undervoltage warning threshold. if a vin_uv_f ault occurs, the input voltage must rise above vin_uv_warn_limit to clear the fault, which provides hysteresis to the fault threshold. in response to the uv_warn_limit being exceeded, the device sets the none of the above and input bits in status_word, sets the vin_uv_warning bit in status_input, and notifies the host. data length in bytes: 2 data format: l11 type : r/w default value: 1.05 x vin_uv_fault_limit pin strap setting units: v range : 0v to 12v vin_uv_fault_limit (59h) definition: sets the v in undervoltage fault threshold. data length in bytes: 2 data format: l11 type: r/w default value: pin strap setting units: v range: 0v to 12v vin_uv_fault_response (5ah) definition: configures the v in undervoltage fault response as defined by the followin g table. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a power_good_on (5eh) definition: sets the voltage threshold for power-good indication. powe r-good asserts with a delay specified in power_good_delay after the output voltage exceeds power_good_on and deasserts when the output voltage is less than vout_uv_warn_limit. data length in bytes: 2 data format: l16u type: r/w default value: 0.9xvout_command pin strap setting units: v ton_delay (60h) definition: sets the delay time from when the device is enabled to the start of v out rise. data length in bytes: 2 data format: l11 type: r/w default value: pin strap setting units: ms range: 0 to 500ms settings actions 80h disable with no retry bfh disable and continuous retry with 70ms delay
isl8272m fn8670 rev.5.00 page 38 of 59 nov 8, 2017 ton_rise (61h) definition: sets the rise time of v out after enable and ton_delay. in multi-module current sharing configuration where ascr is disabled for start up, the rise time of v out can be approximately calculated by equation 1. data length in bytes: 2 data format: l11 type: r/w default value: pin strap setting units: ms range: 0 to 200ms toff_delay (64h) definition: sets the delay time from disable to the start of v out fall. data length in bytes: 2 data format: l11 type: r/w default value: pin strap setting units: ms range: 0 to 500ms toff_fall (65h) definition: sets the soft-off fall time for v out after disable and toff_delay. data length in bytes: 2 data format: l11 type: r/w default value: pin strap setting units: ms range: 0 to 200ms status_byte (78h) definition: returns one byte of information with a summary of the most critical faults. data length in bytes: 1 data format: bit type: read-only default value: 00h units: n/a bit number status bit name meaning 7 busy a fault was declared because the device was busy and unable to respond. 6 off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory or logic fault has occurred. 0 none of the above a fault or warning not listed in bits 7:1 has occurred.
isl8272m fn8670 rev.5.00 page 39 of 59 nov 8, 2017 status_word (79h) definition: returns two bytes of information with a summary of the unit's fault condition. based on the information in these bytes, the host can get more information by reading th e appropriate status registers. the low byte of the status_word is the same register as the status_byte (78h) command. data length in bytes: 2 data format: bit type: read-only default value: 0000h units: n/a status_vout (7ah) definition: returns one data byte with the status of the output voltage. data length in bytes: 1 data format: bit type: read-only default value: 00h units: n/a bit number status bit name meaning 15 vout an output voltage fault or warning has occurred. 14 iout/pout an output current or output power fault or warning has occurred. 13 input an input voltage, input current, or input power fault or warning has occurred. 12 mfg_specific a manufacturer specific fault or warning has occurred. 11 power_good# the power_good signal, if present, is negated. 10 fans a fan or airflow fault or warning has occurred. 9 other a bit in status_other is set. 8 unknown a fault type not given in bits 15:1 of the status_word has been detected. 7 busy a fault was declared because the device was busy and unable to respond. 6 off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory or logic fault has occurred. 0 none of the above a fault or warning not listed in bits 7:1 has occurred. bit number status bit name meaning 7 vout_ov_fault indicates an output overvoltage fault. 6 vout_ov_warning indicates an output overvoltage warning. 5 vout_uv_warning indicates an output undervoltage warning. 4 vout_uv_fault indicates an output undervoltage fault. 3:0 n/a these bits are not used.
isl8272m fn8670 rev.5.00 page 40 of 59 nov 8, 2017 status_iout (7bh) definition: returns one data byte with the status of the output current. data length in bytes: 1 data format: bit type: read-only default value: 00h units: n/a status_input (7ch) definition: returns input voltage and input current status information. data length in bytes: 1 data format: bit type: read-only default value: 00h units: n/a status_temp (7dh) definition: returns one byte of information with a summary of any temperature related faults or warnings. data length in bytes: 1 data format: bit type: read-only default value: 00h units: n/a bit number status bit name meaning 7 iout_oc_fault an output overcurrent fault has occurred. 6 iout_oc_lv_fault an output overcurrent and low voltage fault has occurred. 5 iout_oc_warning an output overcurrent warning has occurred. 4 iout_uc_fault an output undercurrent fault has occurred. 3:0 n/a these bits are not used. bit number status bit name meaning 7 vin_ov_fault an input overvoltage fault has occurred. 6 vin_ov_warning an input overvoltage warning has occurred. 5 vin_uv_warning an input undervoltage warning has occurred. 4 vin_uv_fault an input undervoltage fault has occurred. 3:0 n/a these bits are not used. bit number status bit name meaning 7 ot_fault an over-temperature fault has occurred. 6 ot_warning an over-temperature warning has occurred. 5 ut_warning an under-temperature warning has occurred. 4 ut_fault an under-temperature fault has occurred. 3:0 n/a these bits are not used.
isl8272m fn8670 rev.5.00 page 41 of 59 nov 8, 2017 status_cml (7eh) definition: returns one byte of information with a summary of any communications, logic, and/or memory errors. data length in bytes: 1 data format: bit type: read-only default value: 00h units: n/a status_mfr_specific (80h) definition: returns one byte of information providing the status of the device's voltage moni toring and clock synchronization faults. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a read_vin (88h) definition: returns the input voltage reading. data length in bytes: 2 data format: l11 type: read-only units: v read_vout (8bh) definition: returns the output voltage reading. data length in bytes: 2 data format: l16u type: read-only units: v bit number meaning 7 invalid or unsupported pmbus command was received. 6 the pmbus command was sent with invalid or unsupported data. 5 packet error was detected in the pmbus command. 4:2 not used 1 a pmbus command tried to write to a read-only or protected command, or a communication fault other than the ones listed in this table has occurred. 0not used bit number field name meaning 7:6 reserved reserved. 5 vmon uv warning the voltage on the vmon pin has dropped below 4v. 4 vmon ov warning the voltage on the vmon pin has risen above 5.9v. 3 external switching period fault loss of external clock synchronization has occurred. 2 reserved reserved. 1 vmon uv fault the voltage on the vmon pin has dropped below the level set by vmon_uv_fault_limit. 0 vmon ov fault the voltage on the vmon pin has risen above the level set by vmon_ov_fault_limit.
isl8272m fn8670 rev.5.00 page 42 of 59 nov 8, 2017 read_iout (8ch) definition: returns the output current reading. data length in bytes: 2 data format: l11 type: read-only default value: n/a units: a read_internal_temp (8dh) definition: returns the controller juncti on temperature reading from internal temperature sensor. data length in bytes: 2 data format: l11 type: read-only units: c read_duty_cycle (94h) definition: reports the actual duty cycle of the converter during the enable state. data length in bytes: 2 data format: l11 type: read only units: % read_frequency (95h) definition: reports the actual switching frequency of the converter during the enable state. data length in bytes: 2 data format: l11 type: read only units: khz read_iout_0 (96h) definition: returns the phase 1 current reading. data length in bytes: 2 data format: l11 type: read-only default value: n/a units: a read_iout_1 (97h) definition: returns the phase 2 current reading. data length in bytes: 2 data format: l11 type: read-only default value: n/a units: a
isl8272m fn8670 rev.5.00 page 43 of 59 nov 8, 2017 mfr_id (99h) definition: sets user defined identification. the sum total of char acters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial and user_data_00 plus one byte per comm and cannot exceed 128 characters . this limitation includes multiple writes of this command before a store command. to clea r multiple writes, perform a rest ore, write this command, then perform a store/restore. data length in bytes: user defined data format: ascii type: block r/w default value: null units: n/a mfr_model (9ah) definition: sets a user defined model. the sum total of characte rs in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one byte per comm and cannot exceed 128 characters. this limitation includes multiple writes of this command before a store command. to clea r multiple writes, perform a rest ore, write this command, then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a mfr_revision (9bh) definition: sets a user defined revision. the sum total of characte rs in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one byte per comm and cannot exceed 128 characters. this limitation includes multiple writes of this command before a store command. to clea r multiple writes, perform a rest ore, write this command, then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a mfr_location (9ch) definition: sets a user defined location identifier. the sum tota l of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial and user_data_00 plus one byte per command cannot exceed 128 characters. this limitation includes multiple writes of th is command before a store command. to clea r multiple writes, perform a restore, write this command, then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a mfr_date (9dh) definition: sets a user defined date. the sum total of characters in mfr_id, mfr_model, mfr_revi sion, mfr_location, mfr_date, mfr_serial and user_data_00 plus one byte per command cannot exce ed 128 characters. this limitation includes multiple writes of this command before a store command. to clear multiple wr ites, perform a restore, write this command, then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a reference: n/a
isl8272m fn8670 rev.5.00 page 44 of 59 nov 8, 2017 mfr_serial (9eh) definition: sets a user defined serialized identifier. the sum to tal of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one byte per command cannot ex ceed 128 characters. this limitation includes multiple writes of th is command before a store command. to clea r multiple writes, perform a restore, write this command, then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a legacy_fault_group (a8h) definition: specifies which rail ddc ids should be listened to for fault sp reading with legacy devices. the data sent is a 4-byte, 32-bit, bit vector where every bit represents a rail?s ddc id. a bit set to 1 indicates a device ddc id to which the configured device will respond upon receiving a fault spreading event. in this vector, bit 0 of byte 0 corresponds to the rail with ddc id 0. following throug h, bit 7 of byte 3 corresponds to the rail with ddc id 31. data length in bytes : 4 data format: bit type: r/w default value: 00000000h user_data_00 (b0h) definition: sets user defined data. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one byte per command cannot exceed 128 characters. this limitation includes multiple writes of this command before a store command. to clear multiple wr ites, perform a restore, write this command, then perform a store/restore. data length in bytes: user defined data format: ascii type: block r/w default value: null units: n/a isense_config (d0h) definition: configures current sense circuitry. data length in bytes: 1 data format: bit type: r/w default value: 05h units: n/a bit field name value setting description 7:4 reserved 000 3:2 current sense blanking time 00 192ns sets the blanking time current sense blanking time. 01 256ns 10 412ns 11 640ns 1:0 current sense range 00 low range 25mv 01 mid range 35mv 10 high range 50mv 11 not used
isl8272m fn8670 rev.5.00 page 45 of 59 nov 8, 2017 user_config (d1h) definition: configures several user-level features. this command overrides the config pin settings. data length in bytes: 1 data format: bit type: r/w default value: pin strap setting units: n/a ddc_config (d3h) definition: configures ddc addressing and current sharin g. with pin strap for stand alone configur ation, the ddc rail id is set according to the smbus address. with pin strap for mu lti-module current sharing, the ddc rail id is set according to the number of device s. device position and number of devices in the rail can be programmed as needed. data length in bytes: 2 data format: bit type: r/w default value: pin strap setting units: n/a bit field name value setting description 7 ascr on for start up 0 disabled ascr is disabled for start up. use this for current sharing mode. ascr is enabled for start up. use this for stand alone mode. 1enabled 6:5 reserved 0 reserved 4:3 ramp-up and ramp-down minimum duty cycle 00 0.39% sets the minimum duty-cycle during start-up and shutdown ramp. 01 0.78% 10 1.17% 11 1.56% 2 minimum duty cycle control 0 disable control for minimum duty cycle. 1enable 1power-good pin configuration 0 open drain 0 = pg is open drain output. 1 = pg is push-pull output. 1push-pull 0 reserved 0 bit field name value setting description 15:13 device position 0, 1, 2, 3 sets the device position in a current sharing rail. 0-position 1 1-position 2 2-position 3 3-position 4 12:8 rail id 0 to 31 (00 to 1fh) configures the ddc rail id. 7:4 reserved 0 reserved reserved 3 device internal phase difference 0, 1 sets the internal phase difference of the phase. the 0-phase difference is 180. the 1-phase difference is 0. 2:0 number of devices in rail 1, 3, 5, 7 identifies the number of devices in a current sharing rail. 1-standalone 3-two devices 5-three devices 7-four devices
isl8272m fn8670 rev.5.00 page 46 of 59 nov 8, 2017 power_good_delay (d4h) definition: sets the delay applied between the output exceeding the pg threshold (power_good_on) an d asserting the pg pin. the delay time can range from 0ms up to 500s, in steps of 125ns. a 1ms minimum configured value is recommended to apply proper de-bounce to this signal. data length in bytes: 2 data format: l11 type: r/w default value: 3ms units: ms range: 0 to 5s ascr_config (dfh) definition: allows user configuration of ascr sett ings. ascr gain is analogous to bandwi dth and ascr residual is analogous to damping. to improve load transient response performance, increase ascr gain. to lower transient response overshoot, increase as cr residual. increasing ascr gain can result in increased pwm jitter and should be evaluated in the application circuit. excessive ascr gain can lead to excessive output voltage ripple. increasing ascr residual to improve transient response damping can result in slower recovery times, but will not affect the peak output voltage deviation. typical ascr ga in settings range from 50 to 1000 and asc r residual settings range from 10 to 100. data length in bytes: 4 data format: cus type: r/w default value: pin strap setting sequence (e0h) definition: identifies the rail ddc id of the prequel and sequel rails wh en performing multi-rail sequencing. the device will enable its output when its en or operation enable states, as defined by on_off_config, are set and th e prequel device has issued a power-good event on the ddc bus. the device will disable its output (using the programmed delay values) when the sequel device has issued a power-down event on the ddc bus. the data field is a two-byte value. the most-significant byte co ntains the 5-bit rail ddc id of the prequel device. the least-s ignificant byte contains the 5-bit rail ddc id of the sequel device. the most significant bit of each byte contains the enable of the preq uel or sequel mode. this command overrides the corresponding sequence configuration set by the config pin settings. data length in bytes: 2 data format: bit type: r/w default value: 0000h (prequel and sequel disabled) bit purpose data format value description 31:25 unused 0000000h unused 24 ascr enable bit 1enable 0 disable 23:16 ascr residual setting integer ascr residual 15:0 ascr gain setting integer ascr gain bit field name value setting description 15 prequel enable 0 disable disable, no prequel preceding this rail. 1 enable enable, prequel to this rail is defined by bits 12:8. 14:13 reserved 0 reserved reserved 12:8 prequel rail ddc id 0-31 ddc id set to the ddc id of the prequel rail. 7sequel enable 0 disable disable, no sequel following this rail. 1 enable enable, sequel to this rail is defined by bits 4:0. 6:5 reserved 0 reserved reserved 4:0 sequel rail ddc id 0-31 ddc id set to the ddc id of the sequel rail.
isl8272m fn8670 rev.5.00 page 47 of 59 nov 8, 2017 ddc_group (e2h) definition: configures fault spreading group id and enable, br oadcast operation group id and enable, and broadcast vout_command group id and enable. data length in bytes : 3 data format: bit type: r/w default value: pin strap setting (ignore broadcast vout_command, oper ationn and fault for stand alone operation. enable broadcast vout_command, operation, and fault for current sharing). device_id (e4h) definition: returns the 16-byte (character) device identifier string. data length in bytes: 16 data format: ascii type: block read default value: part number/die revision/firmware revision mfr_iout_oc_fault_response (e5h) definition: configures the i out overcurrent fault response as defined by the following table. the command format is the same as the pmbus standard fault responses except that it sets the overcurrent status bit in status_iout. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a bits purpose value description 23:22 reserved 0 reserved 21 broadcast_vout_command response 1 responds to broadcast_vout_command with same group id. 0ignores broadcast_vout_command. 20:16 broadcast_vout_command group id 0-31d group id sent as data for broadcast broadcast_vout_command events. 15:14 reserved 0 reserved 13 broadcast_operation response 1 responds to broadcast_operation with same group id. 0ignores broadcast_operation. 12:8 broadcast_operation group id 0-31d group id sent as data for broadcast broadcast_operation events. 7:6 reserved 0 reserved 5 power_fail response 1 responds to power_fail events with same group id by shutting down immediately. 0 responds to power_fail events with same group id with sequenced shutdown. 4:0 power_fail group id 0-31d group id sent as data for broadcast power_fail events. settings actions 80h disable with no retry. bfh disable and continuous retry with 70ms delay.
isl8272m fn8670 rev.5.00 page 48 of 59 nov 8, 2017 mfr_iout_uc_fault_response (e6h) definition: configures the i out undercurrent fault response as defined by the foll owing table. the command format is the same as the pmbus standard fault responses except that it se ts the undercurrent status bit in status_iout. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a sync_config (e9h) definition: sets options for sync output configurations. data length in bytes: 1 data format: bit type: r/w default value: pin strap setting settings actions 80h disable with no retry. bfh disable and continuous retry with 70ms delay. settings actions 00h use internal clock. clock frequency is set by pin strap or pmbus command. 02h use internal clock and output internal clock. 04h use external clock.
isl8272m fn8670 rev.5.00 page 49 of 59 nov 8, 2017 snapshot (eah) definition: a 32-byte read-back of parametric and status values. it allows monitoring and status data to be stored to flash following a fault condition. in case of a fault, the last updated values ar e stored to the flash memory. when the snapshot status bit is se t stored, device will no longer automatically capture parametric and status values following fault until stored data are erased. use the snapshot_control command to erase store data and clear the status bit before next ramp up. data erased is not allowed when the module is enabled. data length in bytes: 32 data format: bit field type: block read blank_params (ebh) definition: returns a 16-byte string indicating which parameter values we re either retrieved by the last restore operation or have been written since that time. re ading blank_params immediately after a restore operation allows the user to determine which parameters are stored in that store. a one indicates the parameter is not present in the store and has not been written since t he restore operation. data length in bytes: 16 data format: bit type: block read default value: ff?ffh snapshot_control (f3h) definition: writing a 01h will cause the device to copy the current sn apshot values from nvram to the 32-byte snapshot command parameter. writing a 02h will cause the device to write the curr ent snapshot values to nvram, and writing a 03h will erase all snapshot values from nvram. write (02h) and erase (03h) may only be used when the device is disabled. all other values are ignored. data length in bytes: 1 data format: bit field type: r/w byte byte number value pmbus command format 31:23 reserved reserved 00h 22 flash memory status byte ff - not stored 00 - stored n/a bit 21 manufacturer specific status byte status_mfr_specific (80h) byte 20 cml status byte status_cml (7eh) byte 19 temperature status byte status_temperature (7dh) byte 18 input status byte status_input (7ch) byte 17 i out status byte status_iout (7bh) byte 16 v out status byte status_vout (7ah) byte 15:14 switching frequency read_frequency (95h) l11 13:12 reserved reserved 00h 11:10 internal temperature r ead_internal_temp (8dh) l11 9:8 duty cycle read_duty_cycle (94h) l11 7:6 highest measured output current n/a l11 5:4 output current read_iout (8ch) l11 3:2 output voltage read_vout (8bh) l16u 1:0 input voltage read_vin (88h) l11 value description 01h read snapshot values from nv ram 02h write snapshot values to nv ram 03h erase snapshot values stored in nv ram.
isl8272m fn8670 rev.5.00 page 50 of 59 nov 8, 2017 restore_factory (f4h) definition: restores the device to the hard-coded factory default values and pin strap definitions. the device retains the default and user stores for restoring. security level is changed to level 1 following this command. data length in bytes: 0 data format: n/a type: write only default value: n/a units: n/a mfr_vmon_ov_fault_limit (f5h) definition: reads the vmon ov fault threshold. data length in bytes: 2 data format: l11 type: read only default value: cb00h (6v) units: v range: 4v to 6v mfr_vmon_uv_fault_limit (f6h) definition: reads the vmon uv fault threshold. data length in bytes: 2 data format: l11 type: read only default value: ca00h (4v) units: v range: 4v to 6v mfr_read_vmon (f7h) definition: reads the vmon voltage. data length in bytes: 2 data format: l11 type: read only default value: n/a units: v range: 4v to 6v vmon_ov_fault_response (f8h) definition: reads the vmon ov fault response. data length in bytes: 1 data format: bit type: read only default value: 80h (disable and no retry) units: vmon_uv_fault_response (f9h) definition: reads the vmon uv fault response, which follows vin_uv_fault_response. data length in bytes: 1 data format: bit type: read only default value: 80h (disable and no retry) units: v
isl8272m fn8670 rev.5.00 page 51 of 59 nov 8, 2017 firmware revision history table 10. isl8272m nomenclature guide firmware revision code change description note isl8272-000-fc02 - enhanced fault management during start-up - enhanced iout uc fault management during start-up - enhanced pmbus immunity to noise and lockup - added paged isengain and isenoffset factors which are storable in default memory - added temperature compensation for the paged isengain and isenoffset factors and reduced temperature drift - improved intra-device current balance within the two internal phases - fixed the synchronization issue during vout_command change on-the-fly current sharing conditions - added more pin-strap resistor settings for the cs pin for four-module current sharing conditions - added the capability to change the device internal phase difference from 180 to 0 in ddc_config and optimized module-to- module phase shift in current sharing mode - vmon uv/ov warning value changed recommended for new designs isl8272-000-fc01 initial release not recommended for new designs revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please visit our website to make sure you have the latest revision. date revision change nov 8, 2017 fn8670.5 added clock configurations to ta ble 9, current sharing resistor settings on page 22. status_mfr_specific (80h) pmbus command on page 41 - upda ted command definition and th e meanings of bits 4 and 5. ddc_config (d3h) pmbus command on page 45 - updated bit descriptions. added firmware revision b (fc02) to firmware revision history on page 51 and firmware graphic on page 3. renumbered figures to fix issue in which figure 4 was listed twice. mar 31, 2017 fn8670.4 related literature on page 1 updated. ordering information, page 3: updated note 2 - added tape an d reel option and note 3 - added exemptions 7c-i and 7a. added the notation "a standard 1% resistor is required" to the following sections: -soft-start/stop delay and ramp times, switching frequenc y and pll, loop compensation, input undervoltage lockout (uvlo), smbus module address se lection, active current sharing added "note that fault retry is not supported in the cu rrent sharing configuration." to the following sections: input undervoltage lockout (uvlo), output overvoltage prot ection, output overcurrent protection, thermal overload protection, active current sharing, fault spreading ("note that fault retry is not supported in multiple modules with faul t spreading enabled, such as the current sharing configuration."). smbus communications section on page 17, paragraph added (3rd paragraph) soft-start/stop delay and ramp times section page 17? a paragraph was added (1st paragraph) pmbus use guidelines - added "commands not listed in the pmbus command summary are not allowed for customer use, and are reserved for factory use only. issuing reserv ed commands may result in unexpected operation." pod y58.18x23 revised from rev 1 to rev 3. changes since rev 1: 1) pages 1 and 2 of pod y58.18x23 remain unchanged for this update. 2) deleted remaining pages 3-5 of existing pod and replaced with: new drawings - 2 drawings per page on page 2, in the "size details for the 16 exposed pads" (bot tom view) changed dimension 8.40 (2x) to 8.30 (2x) and 8.00 (2x) to 1.00 (2x). mar 16, 2016 fn8670.3 added ?pmbus use guidelines? on page 29. updated pod y58.18x23 to the latest revision changes are as follows: -detail a on page 1: added reference radius for rounded corners on small i/o pads. jan 14, 2015 fn8670.2 ?electrical specifications? on page 10 under vo ut_accy and vout_read_err: updated unit value from ?% fs? to ?%vout?. updated ?switching frequency and pll? on page 18. sep 17, 2014 fn8670.1 removed the words ?in forced ccm mode? from 2nd paragraph on page 1, which read ?the isl8272m operated in f orced ccm mode with the chargemode? control architecture,... sep 12, 2014 fn8670.0 initial release
fn8670 rev.5.00 page 52 of 59 nov 8, 2017 isl8272m intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2014-2017. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . for a listing of definitions and abbreviations of common terms used in our documents, visit: www.intersil.com/glossary . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support .
fn8670 rev.5.00 page 53 of 59 nov 8, 2017 isl8272m package outline drawing y58.18x23 58 i/o 18mmx23mmx7.5mm custom hda module rev 3, 12/16 15 18 16 17 13 14 11 12 ab ac u v w y aa n p r t 6 9 10 7 84 52 3 h j k l m d e f g a b c 1 terminal tip 7.50 max max 0.025 seating plane side view c 42 x 0.60 0.05 top view 18.00 detail a 0.20 ref 0.20 ref 0.10 c (9x11.5) index area terminal #a1 0.10 c2x 2x 23.00 a b 0.10 c a b 3 3 0.05 c 42 x 0.60 0.05 2 2 1.00 1.00 0.10 c 0.08 c represents the basic land grid pitch. 3. 2. all dimensions are in millimeters. 1. notes: dimensioning and tolerancing per asme y14.5-2009. tolerance for exposed pad e dge location dimension on 4. 5. these 42 i/os are centered in a fixed row and column matrix at 1.0mm pitch bsc. page 3 is 0.1mm. datum a pin a1 indicator c = 0.35 see detail a datum b 16.00 17.20 22.60 0.15 0.10 c a b m 0.40 ref 0.10 c a b m 12.00 bottom view 0.100 r ref m m for the most recent package outline drawing, see y58.18x23 .
fn8670 rev.5.00 page 54 of 59 nov 8, 2017 isl8272m 9.70 2.90 3.60 2.00 5.40 7.00 4.00 6.50 8.60 0.20 0.80 6.60 7.20 2.60 8.50 6.40 2.90 5.10 2.40 1.80 4.40 4.60 6.00 0.40 8.60 6.00 8.10 9.30 9.70 11.30 3.80 3.00 1.20 8.10 9.30 11.30 5.20 6.30 6.00 4.00 3.30 0.00 9.10 6.20 7.20 2.00 5.70 5.50 6.30 6.50 8.80 7.80 2.70 2.30 1.70 1.30 0.70 0.70 1.30 1.70 2.30 5.80 5.20 4.80 4.20 3.80 3.20 9.30 8.70 5.30 4.70 3.30 4.30 3.70 2.70 0.30 0.30 7.30 6.70 9.70 11.30 7.70 2.30 1.00 8.20 6.80 2.00 5.50 6.50 9.10 7.20 9.30 4.30 4.70 5.30 5.70 3.70 0.00 0.70 1.30 7.30 6.70 7.80 8.80 9.70 7.70 6.30 11.30 6.20 4.80 4.20 3.80 3.20 1.80 2.20 2.80 5.20 5.80 0.50 0.50 2.80 2.20 1.20 0.80 0.80 1.20 0.20 0.20 1.80 1.60 (2x) 2.10 (2x) 1.10 (2x) 5.30 (2x) 5.60 7.40 6.40 1.40 (2x) 4.40 6.20 0.60 5.60 4.00 (2x) 4.20 2.00 (2x) 0.80 (2x) 2.20 1.10 5.00 (2x) 2.20 3.50 (2x) 2.60 4.80 (2x) 1.60 (2x) 1.00 (2x) 3.60 8.30 (2x) 3.40 1.00 (2x) 1.30 2.30 4.60 4.40 1.60 (2x) size details for the 16 exposed pads bottom view 1.00 (2x) terminal and pad edge details
fn8670 rev.5.00 page 55 of 59 nov 8, 2017 isl8272m stencil opening center position 0.000 0.000 11.270 2.030 3.590 3.910 5.470 7.810 8.130 9.410 11.270 11.500 11.500 0.530 1.390 1.710 2.500 5.610 6.400 6.720 7.510 7.830 8.770 0.530 1.390 1.710 2.500 5.610 6.400 6.720 7.510 7.830 8.770 9.000 11.500 11.270 9.730 9.410 8.130 7.810 6.530 5.470 3.910 3.590 2.030 7.510 7.830 8.640 8.960 9.770 10.090 11.270 11.500 9.730 9.000 8.570 7.660 7.340 5.240 4.920 4.190 3.870 3.140 2.090 0.230 0.770 1.230 1.910 2.230 2.910 3.230 3.910 4.230 4.910 5.230 5.910 6.230 6.910 9.000 9.000 stencil opening edge position - 1 3.895 5.290 2.820 3.895 4.215 5.290 6.530 6.330 7.790 8.110 9.490 9.810 2.820 5.970 6.430 9.730 9.730 6.330 2.820 4.215 0.000 0.000 0.000 0.000 stencil opening edge position - 2 0.785 3.215 0.215 0.785 4.215 5.215 5.785 6.215 6.785 7.785 9.285 8.715 8.285 7.715 7.285 6.715 6.285 5.715 5.285 4.715 3.715 3.285 2.715 1.715 1.285 0.715 0.285 0.285 0.715 2.715 2.285 8.715 7.285 6.285 5.285 4.285 1.285 0.715 0.285 0.285 0.715 1.285 2.715 1.785 1.785 7.215 7.785 4.785 4.215 9.000 9.000 11.500 11.500 11.500 11.500 9.000 9.000 2.285 4.785 3.785 3.215 2.785 2.215 1.785 1.215 5.785 5.215 0.215 1.215 1.785 2.215 2.785 3.785 4.215 4.785 6.215 6.785 4.285 1.285 3.285 6.215 6.785 1.215 1.215 3.215 3.785 3.715 4.715 5.715 6.715 7.715 9.285 3.285 1.715 8.285 0.000 0.000 8.450 7.215 8.785 8.215
fn8670 rev.5.00 page 56 of 59 nov 8, 2017 isl8272m stencil opening edge 0.000 0.000 6.330 7.960 11.500 6.570 5.890 5.570 4.890 3.890 3.570 2.890 2.570 1.990 1.670 1.160 2.090 2.820 3.140 3.870 4.190 4.430 4.920 5.240 5.970 6.030 6.890 7.210 8.070 11.500 11.500 9.000 9.000 11.500 9.000 9.000 stencil opening edge position - 3 2.770 1.875 1.555 0.660 0.340 0.555 0.875 1.770 2.330 3.495 4.340 4.660 5.505 5.825 6.670 3.175 4.570 8.530 7.640 9.270 0.000 0.000 0.000 0.000 stencil opening edge position - 4 9.070 7.960 7.640 6.530 9.070 7.960 7.640 6.530 2.930 3.840 4.160 5.070 7.170 6.230 3.840 4.160 2.430 3.110 3.430 4.110 5.110 5.430 6.110 8.530 9.270 0.230 1.840 2.160 3.770 4.090 4.570 9.000 9.000 11.500 11.500 9.000 9.000 11.500 11.500 7.170 6.230 6.030 6.705 7.025 7.700 8.020 9.280 10.275 8.570 7.230 5.230 6.740 7.060 8.570 5.070 4.030 5.430 4.430 2.930 9.600 10.595 11.270 6.970 0.000 0.000
fn8670 rev.5.00 page 57 of 59 nov 8, 2017 isl8272m pcb layout pattern 0.000 0.000 stencil opening edge position - 5 6.890 8.070 1.030 2.270 4.030 2.030 3.570 4.430 4.910 8.770 7.810 7.490 6.530 0.430 1.770 6.030 6.705 7.025 7.700 3.030 4.080 4.810 5.130 5.860 6.180 6.910 9.000 9.000 9.280 9.600 10.275 10.595 11.270 11.500 11.500 9.000 9.000 11.500 11.500 5.070 6.030 7.210 3.760 8.020 0.000 pcb land pattern - 1 (for reference) 0.000 9.000 8.800 7.800 7.540 6.690 6.430 5.580 5.320 4.185 3.925 2.790 2.530 1.680 1.420 0.500 1.420 1.680 2.530 2.790 3.925 4.185 5.320 5.580 6.430 6.690 7.540 7.800 8.450 9.000 0.000 11.500 10.950 9.700 9.440 8.100 7.840 6.500 5.500 3.880 3.620 2.000 6.300 7.540 7.800 8.670 8.930 9.800 10.060 11.300 11.500 9.700 0.000 9.000 8.600 7.630 7.370 6.400 6.000 5.210 4.950 4.160 3.900 3.110 2.850 2.060 0.200 0.800 1.200 1.940 2.200 2.940 3.200 3.940 4.200 4.940 5.200 5.940 6.200 6.940 9.000 0.000 9.780 9.700 9.520 8.080 7.820 6.300 11.300 11.500 2.000 3.620 3.880 5.500 6.500 7.840 8.100 9.440 9.700 11.300 11.500 0.500 0.000 8.800
fn8670 rev.5.00 page 58 of 59 nov 8, 2017 isl8272m pcb land pattern - 2 (for reference) 0.000 9.000 5.800 5.200 4.800 4.200 6.800 6.200 3.800 3.200 2.800 2.200 1.800 1.200 0.800 0.200 0.200 0.800 1.200 1.800 2.200 2.800 3.200 3.800 4.200 4.800 9.000 5.200 5.800 0.000 11.500 9.300 8.700 8.300 7.700 7.300 6.700 6.300 5.700 5.300 4.700 4.300 3.700 1.300 0.700 0.300 0.300 0.700 1.300 2.700 3.300 11.500 0.000 9.000 4.800 4.200 3.800 3.200 1.800 1.200 0.200 0.800 1.200 1.800 3.200 3.800 4.200 4.800 6.200 6.800 7.200 7.800 9.000 0.000 11.500 9.300 8.700 8.300 7.700 7.300 6.700 6.300 5.700 5.300 4.700 4.300 3.700 3.300 2.700 2.300 1.700 1.300 0.700 0.300 0.300 0.700 1.300 2.700 3.300 11.500 6.200 6.800 7.200 7.800 8.200 8.800 1.700 2.300 pcb land pattern - 3 (for reference) 0.000 1.800 0.845 0.585 0.370 0.630 1.585 1.845 2.800 9.000 9.000 0.000 6.700 5.795 5.535 4.630 4.370 3.465 3.205 2.300 6.000 6.920 7.180 8.100 11.500 11.500 0.000 11.500 9.300 8.500 7.930 7.670 6.300 11.500 0.000 9.000 6.000 5.210 4.950 4.160 3.900 3.110 2.850 2.060 9.000 1.060 1.700 1.960 2.600 2.860 3.600 3.860 4.600 4.860 5.600 5.860 6.600
fn8670 rev.5.00 page 59 of 59 nov 8, 2017 isl8272m pcb land pattern - 4 (for reference) 9.100 7.930 7.670 6.500 9.000 7.200 6.200 9.000 0.000 11.500 2.900 3.870 4.130 5.100 8.500 9.300 11.500 0.000 9.000 6.140 5.400 5.140 4.400 4.140 3.400 3.140 2.400 7.030 6.770 5.200 8.600 9.000 0.000 11.500 11.300 10.565 10.305 9.570 9.310 7.990 7.730 6.995 6.735 6.000 5.100 4.000 4.130 3.870 2.900 11.500 6.500 7.670 7.930 9.100 0.200 1.870 2.130 3.800 4.060 4.600 5.400 7.000 7.200 8.600 0.000 7.200 6.200 0.000 4.000 5.100 6.000 6.735 6.995 7.730 7.990 9.310 9.570 10.305 10.565 11.300 11.500 11.500 9.000 1.800 0.400 3.000 3.790 4.050 4.840 5.100 5.890 6.150 6.940 9.000 0.000 11.500 8.100 7.180 6.920 6.000 11.500 0.000 9.000 1.000 2.300 pcb land pattern - 5 (for reference) 0.000 8.800 7.780 7.520 6.500 4.940 4.400 3.600 2.000

▲Up To Search▲

Price & Availability of ISL8272MBIRZ

	To Download ISL8272MBIRZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .